void gemattach_sbus(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; struct gem_sbus_softc *gsc = (void *)self; struct gem_softc *sc = &gsc->gsc_gem; /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); /* Pass on the bus tags */ sc->sc_bustag = sa->sa_bustag; sc->sc_dmatag = sa->sa_dmatag; if (sa->sa_nreg < 2) { printf("%s: only %d register sets\n", self->dv_xname, sa->sa_nreg); return; } /* * Map two register banks: * * bank 0: status, config, reset * bank 1: various gem parts * */ if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, (bus_addr_t)sa->sa_reg[0].sbr_offset, (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_h2) != 0) { printf("%s: cannot map registers\n", self->dv_xname); return; } if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, (bus_addr_t)sa->sa_reg[1].sbr_offset, (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_h1) != 0) { printf("%s: cannot map registers\n", self->dv_xname); return; } if (OF_getprop(sa->sa_node, "local-mac-address", sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_arpcom.ac_enaddr); /* * SBUS config */ bus_space_write_4(sa->sa_bustag, sc->sc_h2, GEM_SBUS_CONFIG, GEM_SBUS_CFG_PARITY|GEM_SBUS_CFG_BMODE64); /* Establish interrupt handler */ if (sa->sa_nintr != 0) (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 0, gem_intr, sc, self->dv_xname); gem_config(sc); }
void nep_attach(struct device *parent, struct device *self, void *aux) { struct nep_softc *sc = (struct nep_softc *)self; struct pci_attach_args *pa = aux; struct ifnet *ifp = &sc->sc_ac.ac_if; struct mii_data *mii = &sc->sc_mii; pcireg_t memtype; uint64_t cfg; sc->sc_dmat = pa->pa_dmat; memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT; if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems, 0)) { printf(": can't map registers\n"); return; } sc->sc_port = pa->pa_function; #ifdef __sparc64__ if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_ac.ac_enaddr); #endif printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr)); cfg = nep_read(sc, MIF_CONFIG); cfg &= ~MIF_CONFIG_INDIRECT_MODE; nep_write(sc, MIF_CONFIG, cfg); strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof(ifp->if_xname)); ifp->if_softc = sc; ifp->if_ioctl = nep_ioctl; mii->mii_ifp = ifp; mii->mii_readreg = nep_mii_readreg; mii->mii_writereg = nep_mii_writereg; mii->mii_statchg = nep_mii_statchg; ifmedia_init(&mii->mii_media, 0, nep_mediachange, nep_mediastatus); mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, sc->sc_port, 0); ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); if_attach(ifp); ether_ifattach(ifp); timeout_set(&sc->sc_tick_ch, nep_tick, sc); }
void leattach_lebuffer(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; struct le_softc *lesc = (struct le_softc *)self; struct am7990_softc *sc = &lesc->sc_am7990; struct lebuf_softc *lebuf = (struct lebuf_softc *)parent; /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); lesc->sc_bustag = sa->sa_bustag; lesc->sc_dmatag = sa->sa_dmatag; if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, 0, 0, &lesc->sc_reg)) { printf(": cannot map registers\n"); return; } sc->sc_mem = lebuf->sc_buffer; sc->sc_memsize = lebuf->sc_bufsiz; sc->sc_addr = 0; /* Lance view is offset by buffer location */ lebuf->attached = 1; /* That old black magic... */ sc->sc_conf3 = getpropint(sa->sa_node, "busmaster-regval", LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON); myetheraddr(sc->sc_arpcom.ac_enaddr); sc->sc_copytodesc = am7990_copytobuf_contig; sc->sc_copyfromdesc = am7990_copyfrombuf_contig; sc->sc_copytobuf = am7990_copytobuf_contig; sc->sc_copyfrombuf = am7990_copyfrombuf_contig; sc->sc_zerobuf = am7990_zerobuf_contig; sc->sc_rdcsr = le_lebuffer_rdcsr; sc->sc_wrcsr = le_lebuffer_wrcsr; am7990_config(&lesc->sc_am7990); /* Establish interrupt handler */ if (sa->sa_nintr != 0) (void)bus_intr_establish(lesc->sc_bustag, sa->sa_pri, IPL_NET, 0, am7990_intr, sc, self->dv_xname); }
void cas_attach(struct device *parent, struct device *self, void *aux) { struct pci_attach_args *pa = aux; struct cas_softc *sc = (void *)self; pci_intr_handle_t ih; #ifdef __sparc64__ /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); #endif const char *intrstr = NULL; bus_size_t size; int gotenaddr = 0; sc->sc_rev = PCI_REVISION(pa->pa_class); sc->sc_dmatag = pa->pa_dmat; #define PCI_CAS_BASEADDR 0x10 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, &sc->sc_memt, &sc->sc_memh, NULL, &size, 0) != 0) { printf(": could not map registers\n"); return; } if (cas_pci_enaddr(sc, pa) == 0) gotenaddr = 1; #ifdef __sparc64__ if (!gotenaddr) { if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_arpcom.ac_enaddr); gotenaddr = 1; } #endif #ifdef __powerpc__ if (!gotenaddr) { pci_ether_hw_addr(pa->pa_pc, sc->sc_arpcom.ac_enaddr); gotenaddr = 1; } #endif sc->sc_burst = 16; /* XXX */ if (pci_intr_map(pa, &ih) != 0) { printf(": couldn't map interrupt\n"); bus_space_unmap(sc->sc_memt, sc->sc_memh, size); return; } intrstr = pci_intr_string(pa->pa_pc, ih); sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, cas_intr, sc, self->dv_xname); if (sc->sc_ih == NULL) { printf(": couldn't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); bus_space_unmap(sc->sc_memt, sc->sc_memh, size); return; } printf(": %s", intrstr); /* * call the main configure */ cas_config(sc); }
/* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ void dc_pci_attach(struct device *parent, struct device *self, void *aux) { const char *intrstr = NULL; pcireg_t command; struct dc_pci_softc *psc = (struct dc_pci_softc *)self; struct dc_softc *sc = &psc->psc_softc; struct pci_attach_args *pa = aux; pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; int found = 0; psc->psc_pc = pa->pa_pc; sc->sc_dmat = pa->pa_dmat; pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); sc->dc_csid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); /* * Map control/status registers. */ #ifdef DC_USEIOSPACE if (pci_mapreg_map(pa, DC_PCI_CFBIO, PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, NULL, &psc->psc_mapsize, 0)) { printf(": can't map i/o space\n"); return; } #else if (pci_mapreg_map(pa, DC_PCI_CFBMA, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->dc_btag, &sc->dc_bhandle, NULL, &psc->psc_mapsize, 0)) { printf(": can't map mem space\n"); return; } #endif /* Allocate interrupt */ if (pci_intr_map(pa, &ih)) { printf(": couldn't map interrupt\n"); goto fail_1; } intrstr = pci_intr_string(pc, ih); sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, dc_intr, sc, self->dv_xname); if (sc->sc_ih == NULL) { printf(": couldn't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); goto fail_1; } printf(": %s", intrstr); /* Need this info to decide on a chip type. */ sc->dc_revision = PCI_REVISION(pa->pa_class); /* Get the eeprom width, if possible */ if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LITEON && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LITEON_PNIC)) ; /* PNIC has non-standard eeprom */ else if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_XIRCOM && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143)) ; /* XIRCOM has non-standard eeprom */ else dc_eeprom_width(sc); switch (PCI_VENDOR(pa->pa_id)) { case PCI_VENDOR_DEC: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DEC_21140 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DEC_21142) { found = 1; sc->dc_type = DC_TYPE_21143; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL; dc_read_srom(sc, sc->dc_romwidth); } break; case PCI_VENDOR_INTEL: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_21145) { found = 1; sc->dc_type = DC_TYPE_21145; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL; dc_read_srom(sc, sc->dc_romwidth); } break; case PCI_VENDOR_DAVICOM: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DAVICOM_DM9100 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DAVICOM_DM9102 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_DAVICOM_DM9009) { found = 1; sc->dc_type = DC_TYPE_DM9102; sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; sc->dc_flags |= DC_TX_ALIGN; sc->dc_pmode = DC_PMODE_MII; /* Increase the latency timer value. */ command = pci_conf_read(pc, pa->pa_tag, DC_PCI_CFLT); command &= 0xFFFF00FF; command |= 0x00008000; pci_conf_write(pc, pa->pa_tag, DC_PCI_CFLT, command); } break; case PCI_VENDOR_ADMTEK: case PCI_VENDOR_3COM: case PCI_VENDOR_MICROSOFT: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADMTEK_AL981) { found = 1; sc->dc_type = DC_TYPE_AL981; sc->dc_flags |= DC_TX_USE_TX_INTR; sc->dc_flags |= DC_TX_ADMTEK_WAR; sc->dc_pmode = DC_PMODE_MII; dc_read_srom(sc, sc->dc_romwidth); } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADMTEK_ADM9511 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADMTEK_ADM9513 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADMTEK_AN983 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3COM_3CSHO100BTX || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MICROSOFT_MN130) { found = 1; sc->dc_type = DC_TYPE_AN983; sc->dc_flags |= DC_TX_USE_TX_INTR; sc->dc_flags |= DC_TX_ADMTEK_WAR; sc->dc_flags |= DC_64BIT_HASH; sc->dc_pmode = DC_PMODE_MII; /* Don't read SROM for - auto-loaded on reset */ } break; case PCI_VENDOR_MACRONIX: case PCI_VENDOR_ACCTON: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ACCTON_EN2242) { found = 1; sc->dc_type = DC_TYPE_AN983; sc->dc_flags |= DC_TX_USE_TX_INTR; sc->dc_flags |= DC_TX_ADMTEK_WAR; sc->dc_flags |= DC_64BIT_HASH; sc->dc_pmode = DC_PMODE_MII; /* Don't read SROM for - auto-loaded on reset */ } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MACRONIX_MX98713) { found = 1; if (sc->dc_revision < DC_REVISION_98713A) sc->dc_type = DC_TYPE_98713; if (sc->dc_revision >= DC_REVISION_98713A) { sc->dc_type = DC_TYPE_98713A; sc->dc_flags |= DC_21143_NWAY; } sc->dc_flags |= DC_REDUCED_MII_POLL; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MACRONIX_MX98715 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ACCTON_EN1217) { found = 1; if (sc->dc_revision >= DC_REVISION_98715AEC_C && sc->dc_revision < DC_REVISION_98725) sc->dc_flags |= DC_128BIT_HASH; sc->dc_type = DC_TYPE_987x5; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_MACRONIX_MX98727) { found = 1; sc->dc_type = DC_TYPE_987x5; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; } break; case PCI_VENDOR_COMPEX: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_COMPEX_98713) { found = 1; if (sc->dc_revision < DC_REVISION_98713A) { sc->dc_type = DC_TYPE_98713; sc->dc_flags |= DC_REDUCED_MII_POLL; } if (sc->dc_revision >= DC_REVISION_98713A) sc->dc_type = DC_TYPE_98713A; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; } break; case PCI_VENDOR_LITEON: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LITEON_PNICII) { found = 1; sc->dc_type = DC_TYPE_PNICII; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; sc->dc_flags |= DC_128BIT_HASH; } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LITEON_PNIC) { found = 1; sc->dc_type = DC_TYPE_PNIC; sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; sc->dc_flags |= DC_PNIC_RX_BUG_WAR; sc->dc_pnic_rx_buf = malloc(ETHER_MAX_DIX_LEN * 5, M_DEVBUF, M_NOWAIT); if (sc->dc_pnic_rx_buf == NULL) panic("dc_pci_attach"); if (sc->dc_revision < DC_REVISION_82C169) sc->dc_pmode = DC_PMODE_SYM; } break; case PCI_VENDOR_ASIX: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ASIX_AX88140A) { found = 1; sc->dc_type = DC_TYPE_ASIX; sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; sc->dc_flags |= DC_REDUCED_MII_POLL; sc->dc_pmode = DC_PMODE_MII; } break; case PCI_VENDOR_CONEXANT: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CONEXANT_RS7112) { found = 1; sc->dc_type = DC_TYPE_CONEXANT; sc->dc_flags |= DC_TX_INTR_ALWAYS; sc->dc_flags |= DC_REDUCED_MII_POLL; sc->dc_pmode = DC_PMODE_MII; dc_read_srom(sc, sc->dc_romwidth); } break; case PCI_VENDOR_XIRCOM: if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143) { found = 1; sc->dc_type = DC_TYPE_XIRCOM; sc->dc_flags |= DC_TX_INTR_ALWAYS; sc->dc_flags |= DC_TX_COALESCE; sc->dc_flags |= DC_TX_ALIGN; sc->dc_pmode = DC_PMODE_MII; } break; } if (found == 0) { /* This shouldn't happen if probe has done its job... */ printf(": unknown device: %x:%x\n", PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); goto fail_2; } /* Save the cache line size. */ if (DC_IS_DAVICOM(sc)) sc->dc_cachesize = 0; else sc->dc_cachesize = pci_conf_read(pc, pa->pa_tag, DC_PCI_CFLT) & 0xFF; /* Reset the adapter. */ dc_reset(sc); /* Take 21143 out of snooze mode */ if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { command = pci_conf_read(pc, pa->pa_tag, DC_PCI_CFDD); command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); pci_conf_write(pc, pa->pa_tag, DC_PCI_CFDD, command); } /* * If we discover later (in dc_attach) that we have an * MII with no PHY, we need to have the 21143 drive the LEDs. * Except there are some systems like the NEC VersaPro NoteBook PC * which have no LEDs, and twiddling these bits has adverse effects * on them. (I.e. you suddenly can't get a link.) * * If mii_attach() returns an error, we leave the DC_TULIP_LEDS * bit set, else we clear it. Since our dc(4) driver is split into * bus-dependent and bus-independent parts, we must do set this bit * here while we are able to do PCI configuration reads. */ if (DC_IS_INTEL(sc)) { if (pci_conf_read(pc, pa->pa_tag, DC_PCI_CSID) != 0x80281033) sc->dc_flags |= DC_TULIP_LEDS; } /* * Try to learn something about the supported media. * We know that ASIX and ADMtek and Davicom devices * will *always* be using MII media, so that's a no-brainer. * The tricky ones are the Macronix/PNIC II and the * Intel 21143. */ if (DC_IS_INTEL(sc)) dc_parse_21143_srom(sc); else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { if (sc->dc_type == DC_TYPE_98713) sc->dc_pmode = DC_PMODE_MII; else sc->dc_pmode = DC_PMODE_SYM; } else if (!sc->dc_pmode) sc->dc_pmode = DC_PMODE_MII; #ifdef __sparc64__ { extern void myetheraddr(u_char *); if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_arpcom.ac_enaddr); if (sc->sc_arpcom.ac_enaddr[0] == 0x00 && sc->sc_arpcom.ac_enaddr[1] == 0x03 && sc->sc_arpcom.ac_enaddr[2] == 0xcc) sc->dc_flags |= DC_MOMENCO_BOTCH; sc->sc_hasmac = 1; } #endif #ifdef SRM_MEDIA sc->dc_srm_media = 0; /* Remember the SRM console media setting */ if (DC_IS_INTEL(sc)) { command = pci_conf_read(pc, pa->pa_tag, DC_PCI_CFDD); command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); switch ((command >> 8) & 0xff) { case 3: sc->dc_srm_media = IFM_10_T; break; case 4: sc->dc_srm_media = IFM_10_T | IFM_FDX; break; case 5: sc->dc_srm_media = IFM_100_TX; break; case 6: sc->dc_srm_media = IFM_100_TX | IFM_FDX; break; } if (sc->dc_srm_media) sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; } #endif dc_attach(sc); return; fail_2: pci_intr_disestablish(pc, sc->sc_ih); fail_1: bus_space_unmap(sc->dc_btag, sc->dc_bhandle, psc->psc_mapsize); }
void gemattach_sbus(struct device *parent, struct device *self, void *aux) { struct confargs *ca = aux; struct gem_sbus_softc *gsc = (void *)self; struct gem_softc *sc = &gsc->gsc_gem; /* XXX the following declaration should be elsewhere */ extern void myetheraddr(u_char *); /* Pass on the bus tags */ gsc->gsc_rr = ca->ca_ra.ra_reg[0]; sc->sc_bustag = &gsc->gsc_rr; sc->sc_dmatag = iommu_dmatag; if (ca->ca_ra.ra_nintr < 1) { printf(": no interrupt\n"); return; } if (ca->ca_ra.ra_nreg < 2) { printf(": only %d register sets\n", ca->ca_ra.ra_nreg); return; } sc->sc_variant = GEM_SUN_GEM; /* * Map two register banks: * * bank 0: status, config, reset * bank 1: various gem parts * */ if (bus_space_map(&ca->ca_ra.ra_reg[0], 0, ca->ca_ra.ra_reg[0].rr_len, 0, &sc->sc_h2)) { printf(": can't map registers\n"); return; } if (bus_space_map(&ca->ca_ra.ra_reg[1], 0, ca->ca_ra.ra_reg[1].rr_len, 0, &sc->sc_h1)) { printf(": can't map registers\n"); return; } if (getprop(ca->ca_ra.ra_node, "local-mac-address", sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_arpcom.ac_enaddr); /* * SBUS config */ (void) bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_SBUS_RESET); delay(100); bus_space_write_4(sc->sc_bustag, sc->sc_h2, GEM_SBUS_CONFIG, GEM_SBUS_CFG_BSIZE32); /* Establish interrupt handler */ gsc->gsc_ih.ih_fun = gem_intr; gsc->gsc_ih.ih_arg = sc; intr_establish(ca->ca_ra.ra_intr[0].int_pri, &gsc->gsc_ih, IPL_NET, self->dv_xname); gem_config(sc); }
/* * get the system name */ static void ipid(void) { uint8_t addr[6]; struct ndbtuple *t, *tt; char *p, *attr; struct ndbs s; int f; char buf[Maxpath]; /* use environment, ether addr, or ipaddr to get system name */ if (mysysname == 0) { /* * environment has priority. * * on the sgi power the default system name * is the ip address. ignore that. * */ p = getenv("sysname"); if (p && *p) { attr = ipattr(p); if (strcmp(attr, "ip") != 0) mysysname = strdup(p); } /* * the /net/ndb contains what the network * figured out from DHCP. use that name if * there is one. */ if (mysysname == 0 && netdb != NULL) { ndbreopen(netdb); for (tt = t = ndbparse(netdb); t != NULL; t = t->entry) { if (strcmp(t->attr, "sys") == 0) { mysysname = strdup(t->val); break; } } ndbfree(tt); } /* next network database, ip address, and ether address to find * a name */ if (mysysname == 0) { t = NULL; if (isvalidip(ipa)) free(ndbgetvalue(db, &s, "ip", ipaddr, "sys", &t)); if (t == NULL) { for (f = 0; f < 3; f++) { snprintf(buf, sizeof(buf), "%s/ether%d", mntpt, f); if (myetheraddr(addr, buf) < 0) continue; snprintf(eaddr, sizeof(eaddr), "%E", addr); free(ndbgetvalue(db, &s, "ether", eaddr, "sys", &t)); if (t != NULL) break; } } for (tt = t; tt != NULL; tt = tt->entry) { if (strcmp(tt->attr, "sys") == 0) { mysysname = strdup(tt->val); break; } } ndbfree(t); } /* nothing else worked, use the ip address */ if (mysysname == 0 && isvalidip(ipa)) mysysname = strdup(ipaddr); /* set /dev/sysname if we now know it */ if (mysysname) { f = open("/dev/sysname", O_RDWR); if (f >= 0) { write(f, mysysname, strlen(mysysname)); close(f); } } } }
void gem_attach_pci(struct device *parent, struct device *self, void *aux) { struct pci_attach_args *pa = aux; struct gem_pci_softc *gsc = (void *)self; struct gem_softc *sc = &gsc->gsc_gem; pci_intr_handle_t ih; #ifdef __sparc64__ /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); #endif const char *intrstr = NULL; int type, gotenaddr = 0; gsc->gsc_pc = pa->pa_pc; if (pa->pa_memt) { type = PCI_MAPREG_TYPE_MEM; sc->sc_bustag = pa->pa_memt; } else { type = PCI_MAPREG_TYPE_IO; sc->sc_bustag = pa->pa_iot; } sc->sc_dmatag = pa->pa_dmat; sc->sc_pci = 1; /* XXXXX should all be done in bus_dma. */ switch (PCI_PRODUCT(pa->pa_id)) { case PCI_PRODUCT_SUN_GEMNETWORK: sc->sc_variant = GEM_SUN_GEM; break; case PCI_PRODUCT_SUN_ERINETWORK: sc->sc_variant = GEM_SUN_ERI; break; case PCI_PRODUCT_APPLE_K2_GMAC: sc->sc_variant = GEM_APPLE_K2_GMAC; break; default: sc->sc_variant = GEM_APPLE_GMAC; } #define PCI_GEM_BASEADDR 0x10 if (pci_mapreg_map(pa, PCI_GEM_BASEADDR, type, 0, &gsc->gsc_memt, &gsc->gsc_memh, NULL, &gsc->gsc_memsize, 0) != 0) { printf(": can't map registers\n"); return; } sc->sc_bustag = gsc->gsc_memt; sc->sc_h1 = gsc->gsc_memh; if (bus_space_subregion(sc->sc_bustag, sc->sc_h1, GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE, &sc->sc_h2)) { printf(": unable to create bank 2 subregion\n"); bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize); return; } if (gem_pci_enaddr(sc, pa) == 0) gotenaddr = 1; #ifdef __sparc64__ if (!gotenaddr) { if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0) myetheraddr(sc->sc_arpcom.ac_enaddr); gotenaddr = 1; } #endif #ifdef __powerpc__ if (!gotenaddr) { pci_ether_hw_addr(pa->pa_pc, sc->sc_arpcom.ac_enaddr); gotenaddr = 1; } #endif sc->sc_burst = 16; /* XXX */ if (pci_intr_map(pa, &ih) != 0) { printf(": couldn't map interrupt\n"); bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize); return; } intrstr = pci_intr_string(pa->pa_pc, ih); gsc->gsc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, gem_intr, sc, self->dv_xname); if (gsc->gsc_ih == NULL) { printf(": couldn't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize); return; } printf(": %s", intrstr); /* * call the main configure */ gem_config(sc); }
void leattach_sbus(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; struct le_softc *lesc = (struct le_softc *)self; struct lance_softc *sc = &lesc->sc_am7990.lsc; bus_dma_tag_t dmatag; /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); extern struct cfdriver lebuffer_cd; lesc->sc_bustag = sa->sa_bustag; lesc->sc_dmatag = dmatag = sa->sa_dmatag; if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, BUS_SPACE_MAP_LINEAR, 0, &lesc->sc_reg) != 0) { printf(": cannot map registers\n"); return; } /* * Look for an "unallocated" lebuffer and pair it with * this `le' device on the assumption that we're on * a pre-historic ROM that doesn't establish le<=>lebuffer * parent-child relationships. */ if (lebuffer_cd.cd_ndevs != 0) { struct lebuf_softc *lebuf; int i; for (i = 0; i < lebuffer_cd.cd_ndevs; i++) { lebuf = (struct lebuf_softc *)lebuffer_cd.cd_devs[i]; if (lebuf == NULL || lebuf->attached != 0) continue; sc->sc_mem = lebuf->sc_buffer; sc->sc_memsize = lebuf->sc_bufsiz; /* Lance view is offset by buffer location */ sc->sc_addr = 0; lebuf->attached = 1; /* That old black magic... */ sc->sc_conf3 = getpropint(sa->sa_node, "busmaster-regval", LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON); break; } } if (sc->sc_mem == 0) { bus_dma_segment_t seg; int rseg, error; /* Get a DMA handle */ if ((error = bus_dmamap_create(dmatag, MEMSIZE, 1, MEMSIZE, 0, BUS_DMA_NOWAIT|BUS_DMA_24BIT, &lesc->sc_dmamap)) != 0) { printf(": DMA map create error %d\n", error); return; } /* Allocate DMA buffer */ if ((error = bus_dmamem_alloc(dmatag, MEMSIZE, 0, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT|BUS_DMA_24BIT)) != 0){ printf(": DMA buffer allocation error %d\n", error); return; } /* Map DMA buffer into kernel space */ if ((error = bus_dmamem_map(dmatag, &seg, rseg, MEMSIZE, (caddr_t *)&sc->sc_mem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT|BUS_DMA_24BIT)) != 0) { printf(": DMA buffer map error %d\n", error); bus_dmamem_free(lesc->sc_dmatag, &seg, rseg); return; } /* Load DMA buffer */ if ((error = bus_dmamap_load(dmatag, lesc->sc_dmamap, sc->sc_mem, MEMSIZE, NULL, BUS_DMA_NOWAIT|BUS_DMA_COHERENT|BUS_DMA_24BIT)) != 0) { printf(": DMA buffer map load error %d\n", error); bus_dmamem_free(dmatag, &seg, rseg); bus_dmamem_unmap(dmatag, sc->sc_mem, MEMSIZE); return; } sc->sc_addr = lesc->sc_dmamap->dm_segs[0].ds_addr & 0xffffff; sc->sc_memsize = MEMSIZE; sc->sc_conf3 = LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON; } myetheraddr(sc->sc_arpcom.ac_enaddr); sc->sc_supmedia = lemedia; sc->sc_nsupmedia = nitems(lemedia); sc->sc_defaultmedia = sc->sc_supmedia[sc->sc_nsupmedia - 1]; sc->sc_copytodesc = lance_copytobuf_contig; sc->sc_copyfromdesc = lance_copyfrombuf_contig; sc->sc_copytobuf = lance_copytobuf_contig; sc->sc_copyfrombuf = lance_copyfrombuf_contig; sc->sc_zerobuf = lance_zerobuf_contig; sc->sc_rdcsr = le_sbus_rdcsr; sc->sc_wrcsr = le_sbus_wrcsr; am7990_config(&lesc->sc_am7990); /* Establish interrupt handler */ if (sa->sa_nintr != 0) (void)bus_intr_establish(lesc->sc_bustag, sa->sa_pri, IPL_NET, 0, am7990_intr, sc, self->dv_xname); }
void beattach(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; struct qec_softc *qec = (struct qec_softc *)parent; struct be_softc *sc = (struct be_softc *)self; struct ifnet *ifp = &sc->sc_arpcom.ac_if; struct mii_data *mii = &sc->sc_mii; struct mii_softc *child; int node = sa->sa_node; bus_dma_tag_t dmatag = sa->sa_dmatag; bus_dma_segment_t seg; bus_size_t size; int instance; int rseg, error; u_int32_t v; extern void myetheraddr(u_char *); /* Pass on the bus tags */ sc->sc_bustag = sa->sa_bustag; sc->sc_dmatag = sa->sa_dmatag; if (sa->sa_nreg < 3) { printf("%s: only %d register sets\n", self->dv_xname, sa->sa_nreg); return; } if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, (bus_addr_t)sa->sa_reg[0].sbr_offset, (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) { printf("beattach: cannot map registers\n"); return; } if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, (bus_addr_t)sa->sa_reg[1].sbr_offset, (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) { printf("beattach: cannot map registers\n"); return; } if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot, (bus_addr_t)sa->sa_reg[2].sbr_offset, (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) { printf("beattach: cannot map registers\n"); return; } sc->sc_qec = qec; sc->sc_qr = qec->sc_regs; sc->sc_rev = getpropint(node, "board-version", -1); printf(" rev %x", sc->sc_rev); bestop(sc); sc->sc_channel = getpropint(node, "channel#", -1); if (sc->sc_channel == -1) sc->sc_channel = 0; sc->sc_burst = getpropint(node, "burst-sizes", -1); if (sc->sc_burst == -1) sc->sc_burst = qec->sc_burst; /* Clamp at parent's burst sizes */ sc->sc_burst &= qec->sc_burst; /* Establish interrupt handler */ if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) { printf(": no interrupt established\n"); return; } myetheraddr(sc->sc_arpcom.ac_enaddr); printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); /* * Allocate descriptor ring and buffers. */ /* for now, allocate as many bufs as there are ring descriptors */ sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; /* Get a DMA handle */ if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { printf("%s: DMA map create error %d\n", self->dv_xname, error); return; } /* Allocate DMA buffer */ if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { printf("%s: DMA buffer alloc error %d\n", self->dv_xname, error); return; } /* Map DMA memory in CPU addressable space */ if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { printf("%s: DMA buffer map error %d\n", self->dv_xname, error); bus_dmamem_free(sa->sa_dmatag, &seg, rseg); return; } /* Load the buffer */ if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { printf("%s: DMA buffer map load error %d\n", self->dv_xname, error); bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); bus_dmamem_free(dmatag, &seg, rseg); return; } sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; /* * Initialize our media structures and MII info. */ mii->mii_ifp = ifp; mii->mii_readreg = be_mii_readreg; mii->mii_writereg = be_mii_writereg; mii->mii_statchg = be_mii_statchg; ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); timeout_set(&sc->sc_tick_ch, be_tick, sc); /* * Initialize transceiver and determine which PHY connection to use. */ be_mii_sync(sc); v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); instance = 0; if ((v & MGMT_PAL_EXT_MDIO) != 0) { mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, MII_OFFSET_ANY, 0); child = LIST_FIRST(&mii->mii_phys); if (child == NULL) { /* No PHY attached */ ifmedia_add(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 0, NULL); ifmedia_set(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); } else { /* * Note: we support just one PHY on the external * MII connector. */ #ifdef DIAGNOSTIC if (LIST_NEXT(child, mii_list) != NULL) { printf("%s: spurious MII device %s attached\n", sc->sc_dev.dv_xname, child->mii_dev.dv_xname); } #endif if (child->mii_phy != BE_PHY_EXTERNAL || child->mii_inst > 0) { printf("%s: cannot accommodate MII device %s" " at phy %d, instance %d\n", sc->sc_dev.dv_xname, child->mii_dev.dv_xname, child->mii_phy, child->mii_inst); } else { sc->sc_phys[instance] = child->mii_phy; } /* * XXX - we can really do the following ONLY if the * phy indeed has the auto negotiation capability!! */ ifmedia_set(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); /* Mark our current media setting */ be_pal_gate(sc, BE_PHY_EXTERNAL); instance++; } } if ((v & MGMT_PAL_INT_MDIO) != 0) { /* * The be internal phy looks vaguely like MII hardware, * but not enough to be able to use the MII device * layer. Hence, we have to take care of media selection * ourselves. */ sc->sc_mii_inst = instance; sc->sc_phys[instance] = BE_PHY_INTERNAL; /* Use `ifm_data' to store BMCR bits */ ifmedia_add(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL); ifmedia_add(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), BMCR_S100, NULL); ifmedia_add(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL); printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", self->dv_xname); be_mii_reset(sc, BE_PHY_INTERNAL); /* Only set default medium here if there's no external PHY */ if (instance == 0) { be_pal_gate(sc, BE_PHY_INTERNAL); ifmedia_set(&sc->sc_media, IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); } else be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); } bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); ifp->if_softc = sc; ifp->if_start = bestart; ifp->if_ioctl = beioctl; ifp->if_watchdog = bewatchdog; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; IFQ_SET_READY(&ifp->if_snd); /* Attach the interface. */ if_attach(ifp); ether_ifattach(ifp); }
void leattach_ledma(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; struct le_softc *lesc = (struct le_softc *)self; struct lsi64854_softc *lsi = (struct lsi64854_softc *)parent; struct lance_softc *sc = &lesc->sc_am7990.lsc; bus_dma_tag_t dmatag = sa->sa_dmatag; bus_dma_segment_t seg; int rseg, error; /* XXX the following declarations should be elsewhere */ extern void myetheraddr(u_char *); lesc->sc_bustag = sa->sa_bustag; /* Establish link to `ledma' device */ lesc->sc_dma = lsi; lesc->sc_dma->sc_client = lesc; /* Map device registers */ if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, BUS_SPACE_MAP_LINEAR, 0, &lesc->sc_reg) != 0) { printf("%s @ ledma: cannot map registers\n", self->dv_xname); return; } /* Allocate buffer memory */ sc->sc_memsize = MEMSIZE; /* Get a DMA handle */ if ((error = bus_dmamap_create(dmatag, MEMSIZE, 1, MEMSIZE, LEDMA_BOUNDARY, BUS_DMA_NOWAIT, &lesc->sc_dmamap)) != 0) { printf("%s: DMA map create error %d\n", self->dv_xname, error); return; } /* Allocate DMA buffer */ if ((error = bus_dmamem_alloc(dmatag, MEMSIZE, 0, LEDMA_BOUNDARY, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { printf("%s @ ledma: DMA buffer alloc error %d\n", self->dv_xname, error); return; } /* Map DMA buffer into kernel space */ if ((error = bus_dmamem_map(dmatag, &seg, rseg, MEMSIZE, (caddr_t *)&sc->sc_mem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { printf("%s @ ledma: DMA buffer map error %d\n", self->dv_xname, error); bus_dmamem_free(dmatag, &seg, rseg); return; } /* Load DMA buffer */ if ((error = bus_dmamap_load(dmatag, lesc->sc_dmamap, sc->sc_mem, MEMSIZE, NULL, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { printf("%s: DMA buffer map load error %d\n", self->dv_xname, error); bus_dmamem_free(dmatag, &seg, rseg); bus_dmamem_unmap(dmatag, sc->sc_mem, MEMSIZE); return; } lesc->sc_laddr = lesc->sc_dmamap->dm_segs[0].ds_addr; sc->sc_addr = lesc->sc_laddr & 0xffffff; sc->sc_conf3 = LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON; myetheraddr(sc->sc_arpcom.ac_enaddr); sc->sc_mediachange = lemediachange; sc->sc_mediastatus = lemediastatus; sc->sc_supmedia = lemedia; sc->sc_nsupmedia = nitems(lemedia); sc->sc_defaultmedia = sc->sc_supmedia[sc->sc_nsupmedia - 1]; sc->sc_copytodesc = lance_copytobuf_contig; sc->sc_copyfromdesc = lance_copyfrombuf_contig; sc->sc_copytobuf = lance_copytobuf_contig; sc->sc_copyfrombuf = lance_copyfrombuf_contig; sc->sc_zerobuf = lance_zerobuf_contig; sc->sc_rdcsr = le_ledma_rdcsr; sc->sc_wrcsr = le_ledma_wrcsr; sc->sc_hwinit = le_ledma_hwinit; sc->sc_nocarrier = le_ledma_nocarrier; sc->sc_hwreset = le_ledma_hwreset; /* Establish interrupt handler */ if (sa->sa_nintr != 0) (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 0, am7990_intr, sc, self->dv_xname); am7990_config(&lesc->sc_am7990); /* now initialize DMA */ le_ledma_hwreset(sc); }
void tsec_attach(struct device *parent, struct device *self, void *aux) { struct tsec_softc *sc = (void *)self; struct obio_attach_args *oa = aux; struct ifnet *ifp; int phy, n; if (OF_getprop(oa->oa_node, "phy-handle", &phy, sizeof(phy)) == sizeof(phy)) { int node, reg; node = tsec_find_phy(OF_peer(0), phy); if (node == -1 || OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) { printf(": can't find PHY\n"); return; } oa->oa_phy = reg; } /* Map registers for TSEC1 & TSEC2 if they're not mapped yet. */ if (oa->oa_iot != tsec_iot) { tsec_iot = oa->oa_iot; if (bus_space_map(tsec_iot, oa->oa_offset & 0xffffc000, 8192, 0, &tsec_ioh)) { printf(": can't map registers\n"); return; } } sc->sc_iot = tsec_iot; sc->sc_dmat = oa->oa_dmat; /* Ethernet Controller registers. */ bus_space_subregion(tsec_iot, tsec_ioh, oa->oa_offset & 0x3fff, 3072, &sc->sc_ioh); /* MII Management registers. */ bus_space_subregion(tsec_iot, tsec_ioh, 0, 3072, &sc->sc_mii_ioh); myetheraddr(sc->sc_lladdr); printf(": address %s\n", ether_sprintf(sc->sc_lladdr)); timeout_set(&sc->sc_tick, tsec_tick, sc); ifp = &sc->sc_ac.ac_if; ifp->if_softc = sc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = tsec_ioctl; ifp->if_start = tsec_start; ifp->if_watchdog = tsec_watchdog; IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_NTXDESC - 1); IFQ_SET_READY(&ifp->if_snd); bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); m_clsetwms(ifp, MCLBYTES, 0, TSEC_NRXDESC); ifp->if_capabilities = IFCAP_VLAN_MTU; sc->sc_mii.mii_ifp = ifp; sc->sc_mii.mii_readreg = tsec_mii_readreg; sc->sc_mii.mii_writereg = tsec_mii_writereg; sc->sc_mii.mii_statchg = tsec_mii_statchg; ifmedia_init(&sc->sc_media, 0, tsec_media_change, tsec_media_status); tsec_reset(sc); /* Reset management. */ tsec_write(sc, TSEC_MIIMCFG, TSEC_MIIMCFG_RESET); tsec_write(sc, TSEC_MIIMCFG, 0x00000003); for (n = 0; n < 100; n++) { if ((tsec_read(sc, TSEC_MIIMIND) & TSEC_MIIMIND_BUSY) == 0) break; } mii_attach(self, &sc->sc_mii, 0xffffffff, oa->oa_phy, MII_OFFSET_ANY, 0); if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { printf("%s: no PHY found!\n", sc->sc_dev.dv_xname); ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); } else ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); if_attach(ifp); ether_ifattach(ifp); intr_establish(oa->oa_ivec, IST_LEVEL, IPL_NET, tsec_txintr, sc, sc->sc_dev.dv_xname); intr_establish(oa->oa_ivec + 1, IST_LEVEL, IPL_NET, tsec_rxintr, sc, sc->sc_dev.dv_xname); intr_establish(oa->oa_ivec + 2, IST_LEVEL, IPL_NET, tsec_errintr, sc, sc->sc_dev.dv_xname); }