int sm_register_device(struct mtd_info *mtd, int smartmedia)
{
struct nand_chip *chip = mtd->priv;
int ret;
chip->options |= NAND_SKIP_BBTSCAN;
/* Scan for card properties */
ret = nand_scan_ident(mtd, 1, smartmedia ?
nand_smartmedia_flash_ids : nand_xd_flash_ids);
if (ret)
return ret;
/* Bad block marker position */
chip->badblockpos = 0x05;
chip->badblockbits = 7;
chip->block_markbad = sm_block_markbad;
/* ECC layout */
if (mtd->writesize == SM_SECTOR_SIZE)
chip->ecc.layout = &nand_oob_sm;
else if (mtd->writesize == SM_SMALL_PAGE)
chip->ecc.layout = &nand_oob_sm_small;
else
return -ENODEV;
ret = nand_scan_tail(mtd);
if (ret)
return ret;
return mtd_device_register(mtd, NULL, 0);
}
/**
* nand_scan - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
* @maxchips: Number of chips to scan for
*
* This fills out all the uninitialized function pointers
* with the defaults.
* The flash ID is read and the mtd/chip structures are
* filled with the appropriate values.
* The mtd->owner field must be set to the module of the caller
*
*/
static int stm_nand_scan(struct mtd_info *mtd, int maxchips)
{
int ret;
/*
* Perform the first phase of the normal nand_scan() function.
* It reads the flash ID and sets up MTD fields accordingly.
*/
ret = nand_scan_ident(mtd, maxchips);
if (ret)
return ret;
/*
* Now that we have probed the physical NAND device, and we now know
* the *actual* device ID, we can complete any other ST40-specific
* structure fields properly (e.g. nand->ecc.layout).
*/
stm_nand_scan_post_ident(mtd);
/*
* Perform the second phase of the normal nand_scan() function.
* If fills out the remaining uninitialized function pointers.
*/
ret = nand_scan_tail(mtd);
if (ret)
return ret;
/*
* Finally, perform any post-scanning initialization we want to do.
*/
stm_nand_scan_post_tail(mtd);
return ret;
}
void board_nand_init(void)
{
struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
int ret;
/* Set all BOARDSPECIFIC (actually core-specific) fields */
lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
/* do not set init_size: nand_base.c will read sizes from chip */
lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
/* do not set setup_read_retry: this is NAND-chip-specific */
/* do not set chip_delay: we have dev_ready defined. */
lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
/* Set needed ECC fields */
lpc32xx_chip.ecc.mode = NAND_ECC_HW;
lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
lpc32xx_chip.ecc.size = 512;
lpc32xx_chip.ecc.bytes = 10;
lpc32xx_chip.ecc.strength = 4;
lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
/* BBT options: read from last two pages */
lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
| NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
| NAND_BBT_WRITE;
/* Initialize NAND interface */
lpc32xx_nand_init();
/* identify chip */
ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
if (ret) {
error("nand_scan_ident returned %i", ret);
return;
}
/* finish scanning the chip */
ret = nand_scan_tail(mtd);
if (ret) {
error("nand_scan_tail returned %i", ret);
return;
}
/* chip is good, register it */
ret = nand_register(0, mtd);
if (ret)
error("nand_register returned %i", ret);
}
static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
int ret;
ret = nand_scan_ident(mtd, 1);
if (!ret) {
if (mtd->writesize >= 512) {
chip->ecc.size = mtd->writesize;
chip->ecc.bytes = 3 * (mtd->writesize / 256);
}
ret = nand_scan_tail(mtd);
}
return ret;
}
static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
int ret;
ret = nand_scan_ident(mtd, 1, NULL);
if (!ret) {
if (mtd->writesize >= 512) {
/* Hardware ECC 6 byte ECC per 512 Byte data */
chip->ecc.size = 512;
chip->ecc.bytes = 6;
}
ret = nand_scan_tail(mtd);
}
return ret;
}
/*
* Probe for NAND controller
*/
static int __init lpc32xx_nand_probe(struct platform_device *pdev)
{
struct lpc32xx_nand_host *host;
struct mtd_info *mtd;
struct nand_chip *chip;
struct resource *rc;
int res;
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (rc == NULL) {
dev_err(&pdev->dev,"No memory resource found for"
" device\n");
return -ENXIO;
}
/* Allocate memory for the device structure (and zero it) */
host = kzalloc(sizeof(struct lpc32xx_nand_host), GFP_KERNEL);
if (!host) {
dev_err(&pdev->dev,"failed to allocate device structure\n");
return -ENOMEM;
}
host->io_base_dma = (dma_addr_t) rc->start;
host->io_base = ioremap(rc->start, rc->end - rc->start + 1);
if (host->io_base == NULL) {
dev_err(&pdev->dev,"ioremap failed\n");
res = -EIO;
goto err_exit1;
}
host->ncfg = pdev->dev.platform_data;
if (!host->ncfg) {
dev_err(&pdev->dev,"Missing platform data\n");
res = -ENOENT;
goto err_exit1;
}
mtd = &host->mtd;
chip = &host->nand_chip;
chip->priv = host;
mtd->priv = chip;
mtd->owner = THIS_MODULE;
mtd->dev.parent = &pdev->dev;
/* Get NAND clock */
host->clk = clk_get(&pdev->dev, "nand_ck");
if (IS_ERR(host->clk)) {
dev_err(&pdev->dev,"Clock failure\n");
res = -ENOENT;
goto err_exit2;
}
clk_enable(host->clk);
/* Set NAND IO addresses and command/ready functions */
chip->IO_ADDR_R = SLC_DATA(host->io_base);
chip->IO_ADDR_W = SLC_DATA(host->io_base);
chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
chip->dev_ready = lpc32xx_nand_device_ready;
chip->chip_delay = 20; /* 20us command delay time */
/* Init NAND controller */
lpc32xx_nand_setup(host);
lpc32xx_wp_disable(host);
platform_set_drvdata(pdev, host);
/* NAND callbacks for LPC32xx SLC hardware */
chip->ecc.mode = NAND_ECC_HW_SYNDROME;
chip->read_byte = lpc32xx_nand_read_byte;
chip->read_buf = lpc32xx_nand_read_buf;
chip->write_buf = lpc32xx_nand_write_buf;
chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
chip->ecc.correct = nand_correct_data;
chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
chip->verify_buf = lpc32xx_verify_buf;
/*
* Allocate a large enough buffer for a single huge page plus
* extra space for the spare area and ECC storage area
*/
host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
host->data_buf = dma_alloc_coherent(&pdev->dev, host->dma_buf_len,
&host->data_buf_dma, GFP_KERNEL);
if (host->data_buf == NULL) {
dev_err(&pdev->dev, "Error allocating memory\n");
res = -ENOMEM;
goto err_exit3;
}
/* Get free DMA channel and alloc DMA descriptor link list */
res = lpc32xx_nand_dma_setup(host, LPC32XX_MAX_DMA_DESCRIPTORS);
if(res) {
res = -EIO;
goto err_exit4;
}
init_waitqueue_head(&host->dma_waitq);
/* Find NAND device */
if (nand_scan_ident(mtd, 1)) {
res = -ENXIO;
goto err_exit5;
}
/* OOB and ECC CPU and DMA work areas */
host->ecc_buf_dma = host->data_buf_dma + LPC32XX_DMA_DATA_SIZE;
host->ecc_buf = (uint32_t *) (host->data_buf + LPC32XX_DMA_DATA_SIZE);
/*
* Small page FLASH has a unique OOB layout, but large and huge
* page FLASH use the standard layout. Small page FLASH uses a
* custom BBT marker layout.
*/
if (mtd->writesize <= 512)
chip->ecc.layout = &lpc32xx_nand_oob_16;
/* These sizes remain the same regardless of page size */
chip->ecc.size = 256;
chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
chip->ecc.prepad = chip->ecc.postpad = 0;
/* Avoid extra scan if using BBT, setup BBT support */
if (host->ncfg->use_bbt) {
chip->options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
/*
* Use a custom BBT marker setup for small page FLASH that
* won't interfere with the ECC layout. Large and huge page
* FLASH use the standard layout.
*/
if (mtd->writesize <= 512) {
chip->bbt_td = &bbt_smallpage_main_descr;
chip->bbt_md = &bbt_smallpage_mirror_descr;
}
}
/*
* Fills out all the uninitialized function pointers with the defaults
*/
if (nand_scan_tail(mtd)) {
res = -ENXIO;
goto err_exit5;
}
/* Standard layout in FLASH for bad block tables */
if (host->ncfg->use_bbt) {
if (nand_default_bbt(mtd) < 0)
dev_err(&pdev->dev, "Error initializing default bad"
" block tables\n");
}
res = lpc32xx_add_partitions(host);
if (!res)
return res;
nand_release(mtd);
err_exit5:
/* Free the DMA channel used by us */
lpc32xx_dma_ch_disable(host->dmach);
lpc32xx_dma_dealloc_llist(host->dmach);
lpc32xx_dma_ch_put(host->dmach);
host->dmach = -1;
err_exit4:
dma_free_coherent(&pdev->dev, host->dma_buf_len,
host->data_buf, host->data_buf_dma);
err_exit3:
clk_disable(host->clk);
clk_put(host->clk);
platform_set_drvdata(pdev, NULL);
err_exit2:
lpc32xx_wp_enable(host);
iounmap(host->io_base);
err_exit1:
kfree(host);
return res;
}
/*
* Probe for NAND controller
*/
static int lpc32xx_nand_probe(struct platform_device *pdev)
{
struct lpc32xx_nand_host *host;
struct mtd_info *mtd;
struct nand_chip *chip;
struct resource *rc;
struct mtd_part_parser_data ppdata = {};
int res;
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (rc == NULL) {
dev_err(&pdev->dev, "No memory resource found for device\n");
return -EBUSY;
}
/* Allocate memory for the device structure (and zero it) */
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
if (!host)
return -ENOMEM;
host->io_base_dma = rc->start;
host->io_base = devm_ioremap_resource(&pdev->dev, rc);
if (IS_ERR(host->io_base))
return PTR_ERR(host->io_base);
if (pdev->dev.of_node)
host->ncfg = lpc32xx_parse_dt(&pdev->dev);
if (!host->ncfg) {
dev_err(&pdev->dev,
"Missing or bad NAND config from device tree\n");
return -ENOENT;
}
if (host->ncfg->wp_gpio == -EPROBE_DEFER)
return -EPROBE_DEFER;
if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
host->ncfg->wp_gpio, "NAND WP")) {
dev_err(&pdev->dev, "GPIO not available\n");
return -EBUSY;
}
lpc32xx_wp_disable(host);
host->pdata = dev_get_platdata(&pdev->dev);
mtd = &host->mtd;
chip = &host->nand_chip;
chip->priv = host;
mtd->priv = chip;
mtd->owner = THIS_MODULE;
mtd->dev.parent = &pdev->dev;
/* Get NAND clock */
host->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(host->clk)) {
dev_err(&pdev->dev, "Clock failure\n");
res = -ENOENT;
goto err_exit1;
}
clk_enable(host->clk);
/* Set NAND IO addresses and command/ready functions */
chip->IO_ADDR_R = SLC_DATA(host->io_base);
chip->IO_ADDR_W = SLC_DATA(host->io_base);
chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
chip->dev_ready = lpc32xx_nand_device_ready;
chip->chip_delay = 20; /* 20us command delay time */
/* Init NAND controller */
lpc32xx_nand_setup(host);
platform_set_drvdata(pdev, host);
/* NAND callbacks for LPC32xx SLC hardware */
chip->ecc.mode = NAND_ECC_HW_SYNDROME;
chip->read_byte = lpc32xx_nand_read_byte;
chip->read_buf = lpc32xx_nand_read_buf;
chip->write_buf = lpc32xx_nand_write_buf;
chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
chip->ecc.correct = nand_correct_data;
chip->ecc.strength = 1;
chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
/*
* Allocate a large enough buffer for a single huge page plus
* extra space for the spare area and ECC storage area
*/
host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
GFP_KERNEL);
if (host->data_buf == NULL) {
res = -ENOMEM;
goto err_exit2;
}
res = lpc32xx_nand_dma_setup(host);
if (res) {
res = -EIO;
goto err_exit2;
}
/* Find NAND device */
if (nand_scan_ident(mtd, 1, NULL)) {
res = -ENXIO;
goto err_exit3;
}
/* OOB and ECC CPU and DMA work areas */
host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
/*
* Small page FLASH has a unique OOB layout, but large and huge
* page FLASH use the standard layout. Small page FLASH uses a
* custom BBT marker layout.
*/
if (mtd->writesize <= 512)
chip->ecc.layout = &lpc32xx_nand_oob_16;
/* These sizes remain the same regardless of page size */
chip->ecc.size = 256;
chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
chip->ecc.prepad = chip->ecc.postpad = 0;
/* Avoid extra scan if using BBT, setup BBT support */
if (host->ncfg->use_bbt) {
chip->bbt_options |= NAND_BBT_USE_FLASH;
/*
* Use a custom BBT marker setup for small page FLASH that
* won't interfere with the ECC layout. Large and huge page
* FLASH use the standard layout.
*/
if (mtd->writesize <= 512) {
chip->bbt_td = &bbt_smallpage_main_descr;
chip->bbt_md = &bbt_smallpage_mirror_descr;
}
}
/*
* Fills out all the uninitialized function pointers with the defaults
*/
if (nand_scan_tail(mtd)) {
res = -ENXIO;
goto err_exit3;
}
mtd->name = "nxp_lpc3220_slc";
ppdata.of_node = pdev->dev.of_node;
res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
host->ncfg->num_parts);
if (!res)
return res;
nand_release(mtd);
err_exit3:
dma_release_channel(host->dma_chan);
err_exit2:
clk_disable(host->clk);
err_exit1:
lpc32xx_wp_enable(host);
return res;
}
int denali_init(struct denali_nand_info *denali)
{
int ret;
if (denali->platform == INTEL_CE4100) {
/* Due to a silicon limitation, we can only support
* ONFI timing mode 1 and below.
*/
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
return -EINVAL;
}
}
/* Is 32-bit DMA supported? */
ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
if (ret) {
pr_err("Spectra: no usable DMA configuration\n");
return ret;
}
denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
DENALI_BUF_SIZE,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
return -EIO;
}
denali->mtd.dev.parent = denali->dev;
denali_hw_init(denali);
denali_drv_init(denali);
/* denali_isr register is done after all the hardware
* initilization is finished*/
if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
DENALI_NAND_NAME, denali)) {
pr_err("Spectra: Unable to allocate IRQ\n");
return -ENODEV;
}
/* now that our ISR is registered, we can enable interrupts */
denali_set_intr_modes(denali, true);
denali->mtd.name = "denali-nand";
denali->mtd.owner = THIS_MODULE;
denali->mtd.priv = &denali->nand;
/* register the driver with the NAND core subsystem */
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.waitfunc = denali_waitfunc;
/* scan for NAND devices attached to the controller
* this is the first stage in a two step process to register
* with the nand subsystem */
if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto failed_req_irq;
}
/* MTD supported page sizes vary by kernel. We validate our
* kernel supports the device here.
*/
if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
ret = -ENODEV;
pr_err("Spectra: device size not supported by this version of MTD.");
goto failed_req_irq;
}
/* support for multi nand
* MTD known nothing about multi nand,
* so we should tell it the real pagesize
* and anything necessery
*/
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
denali->nand.chipsize <<= (denali->devnum - 1);
denali->nand.page_shift += (denali->devnum - 1);
denali->nand.pagemask = (denali->nand.chipsize >>
denali->nand.page_shift) - 1;
denali->nand.bbt_erase_shift += (denali->devnum - 1);
denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
denali->nand.chip_shift += (denali->devnum - 1);
denali->mtd.writesize <<= (denali->devnum - 1);
denali->mtd.oobsize <<= (denali->devnum - 1);
denali->mtd.erasesize <<= (denali->devnum - 1);
denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
denali->bbtskipbytes *= denali->devnum;
/* second stage of the NAND scan
* this stage requires information regarding ECC and
* bad block management. */
/* Bad block management */
denali->nand.bbt_td = &bbt_main_descr;
denali->nand.bbt_md = &bbt_mirror_descr;
/* skip the scan for now until we have OOB read and write support */
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
denali->nand.options |= NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
/* Denali Controller only support 15bit and 8bit ECC in MRST,
* so just let controller do 15bit ECC for MLC and 8bit ECC for
* SLC if possible.
* */
if (!nand_is_slc(&denali->nand) &&
(denali->mtd.oobsize > (denali->bbtskipbytes +
ECC_15BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE)))) {
/* if MLC OOB size is large enough, use 15bit ECC*/
denali->nand.ecc.strength = 15;
denali->nand.ecc.layout = &nand_15bit_oob;
denali->nand.ecc.bytes = ECC_15BITS;
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
ECC_8BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE))) {
pr_err("Your NAND chip OOB is not large enough to \
contain 8bit ECC correction codes");
goto failed_req_irq;
} else {
static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
int ret = -ENODEV;
resource_size_t csr_base, mem_base;
unsigned long csr_len, mem_len;
struct denali_nand_info *denali;
denali = kzalloc(sizeof(*denali), GFP_KERNEL);
if (!denali)
return -ENOMEM;
ret = pci_enable_device(dev);
if (ret) {
printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
goto failed_alloc_memery;
}
if (id->driver_data == INTEL_CE4100) {
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
printk(KERN_ERR "Intel CE4100 only supports"
" ONFI timing mode 1 or below\n");
ret = -EINVAL;
goto failed_enable_dev;
}
denali->platform = INTEL_CE4100;
mem_base = pci_resource_start(dev, 0);
mem_len = pci_resource_len(dev, 1);
csr_base = pci_resource_start(dev, 1);
csr_len = pci_resource_len(dev, 1);
} else {
denali->platform = INTEL_MRST;
csr_base = pci_resource_start(dev, 0);
csr_len = pci_resource_len(dev, 0);
mem_base = pci_resource_start(dev, 1);
mem_len = pci_resource_len(dev, 1);
if (!mem_len) {
mem_base = csr_base + csr_len;
mem_len = csr_len;
}
}
ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
if (ret) {
printk(KERN_ERR "Spectra: no usable DMA configuration\n");
goto failed_enable_dev;
}
denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf,
DENALI_BUF_SIZE,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) {
dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
goto failed_enable_dev;
}
pci_set_master(dev);
denali->dev = &dev->dev;
denali->mtd.dev.parent = &dev->dev;
ret = pci_request_regions(dev, DENALI_NAND_NAME);
if (ret) {
printk(KERN_ERR "Spectra: Unable to request memory regions\n");
goto failed_dma_map;
}
denali->flash_reg = ioremap_nocache(csr_base, csr_len);
if (!denali->flash_reg) {
printk(KERN_ERR "Spectra: Unable to remap memory region\n");
ret = -ENOMEM;
goto failed_req_regions;
}
denali->flash_mem = ioremap_nocache(mem_base, mem_len);
if (!denali->flash_mem) {
printk(KERN_ERR "Spectra: ioremap_nocache failed!");
ret = -ENOMEM;
goto failed_remap_reg;
}
denali_hw_init(denali);
denali_drv_init(denali);
if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
DENALI_NAND_NAME, denali)) {
printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
ret = -ENODEV;
goto failed_remap_mem;
}
denali_set_intr_modes(denali, true);
pci_set_drvdata(dev, denali);
denali->mtd.name = "denali-nand";
denali->mtd.owner = THIS_MODULE;
denali->mtd.priv = &denali->nand;
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.waitfunc = denali_waitfunc;
if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto failed_req_irq;
}
if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
ret = -ENODEV;
printk(KERN_ERR "Spectra: device size not supported by this "
"version of MTD.");
goto failed_req_irq;
}
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
denali->nand.chipsize <<= (denali->devnum - 1);
denali->nand.page_shift += (denali->devnum - 1);
denali->nand.pagemask = (denali->nand.chipsize >>
denali->nand.page_shift) - 1;
denali->nand.bbt_erase_shift += (denali->devnum - 1);
denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
denali->nand.chip_shift += (denali->devnum - 1);
denali->mtd.writesize <<= (denali->devnum - 1);
denali->mtd.oobsize <<= (denali->devnum - 1);
denali->mtd.erasesize <<= (denali->devnum - 1);
denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
denali->bbtskipbytes *= denali->devnum;
denali->nand.bbt_td = &bbt_main_descr;
denali->nand.bbt_md = &bbt_mirror_descr;
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
denali->nand.options |= NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
if (denali->nand.cellinfo & 0xc &&
(denali->mtd.oobsize > (denali->bbtskipbytes +
ECC_15BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE)))) {
denali->nand.ecc.strength = 15;
denali->nand.ecc.layout = &nand_15bit_oob;
denali->nand.ecc.bytes = ECC_15BITS;
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
ECC_8BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE))) {
printk(KERN_ERR "Your NAND chip OOB is not large enough to"
" contain 8bit ECC correction codes");
goto failed_req_irq;
} else {
denali->nand.ecc.strength = 8;
denali->nand.ecc.layout = &nand_8bit_oob;
denali->nand.ecc.bytes = ECC_8BITS;
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
}
denali->nand.ecc.bytes *= denali->devnum;
denali->nand.ecc.strength *= denali->devnum;
denali->nand.ecc.layout->eccbytes *=
denali->mtd.writesize / ECC_SECTOR_SIZE;
denali->nand.ecc.layout->oobfree[0].offset =
denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
denali->nand.ecc.layout->oobfree[0].length =
denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
denali->bbtskipbytes;
denali->totalblks = denali->mtd.size >>
denali->nand.phys_erase_shift;
denali->blksperchip = denali->totalblks / denali->nand.numchips;
denali->nand.ecc.calculate = denali_ecc_calculate;
denali->nand.ecc.correct = denali_ecc_correct;
denali->nand.ecc.hwctl = denali_ecc_hwctl;
denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
denali->nand.ecc.write_page_raw = denali_write_page_raw;
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
denali->nand.erase_cmd = denali_erase;
if (nand_scan_tail(&denali->mtd)) {
ret = -ENXIO;
goto failed_req_irq;
}
ret = mtd_device_register(&denali->mtd, NULL, 0);
if (ret) {
dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
ret);
goto failed_req_irq;
}
return 0;
failed_req_irq:
denali_irq_cleanup(dev->irq, denali);
failed_remap_mem:
iounmap(denali->flash_mem);
failed_remap_reg:
iounmap(denali->flash_reg);
failed_req_regions:
pci_release_regions(dev);
failed_dma_map:
dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
DMA_BIDIRECTIONAL);
failed_enable_dev:
pci_disable_device(dev);
failed_alloc_memery:
kfree(denali);
return ret;
}
/* driver entry point */
static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
int ret = -ENODEV;
resource_size_t csr_base, mem_base;
unsigned long csr_len, mem_len;
struct denali_nand_info *denali;
denali = kzalloc(sizeof(*denali), GFP_KERNEL);
if (!denali)
return -ENOMEM;
ret = pci_enable_device(dev);
if (ret) {
printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
goto failed_alloc_memery;
}
if (id->driver_data == INTEL_CE4100) {
/* Due to a silicon limitation, we can only support
* ONFI timing mode 1 and below.
*/
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
printk(KERN_ERR "Intel CE4100 only supports"
" ONFI timing mode 1 or below\n");
ret = -EINVAL;
goto failed_enable_dev;
}
denali->platform = INTEL_CE4100;
mem_base = pci_resource_start(dev, 0);
mem_len = pci_resource_len(dev, 1);
csr_base = pci_resource_start(dev, 1);
csr_len = pci_resource_len(dev, 1);
} else {
denali->platform = INTEL_MRST;
csr_base = pci_resource_start(dev, 0);
csr_len = pci_resource_len(dev, 0);
mem_base = pci_resource_start(dev, 1);
mem_len = pci_resource_len(dev, 1);
if (!mem_len) {
mem_base = csr_base + csr_len;
mem_len = csr_len;
}
}
/* Is 32-bit DMA supported? */
ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
if (ret) {
printk(KERN_ERR "Spectra: no usable DMA configuration\n");
goto failed_enable_dev;
}
denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf,
DENALI_BUF_SIZE,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) {
dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
goto failed_enable_dev;
}
pci_set_master(dev);
denali->dev = &dev->dev;
denali->mtd.dev.parent = &dev->dev;
ret = pci_request_regions(dev, DENALI_NAND_NAME);
if (ret) {
printk(KERN_ERR "Spectra: Unable to request memory regions\n");
goto failed_dma_map;
}
denali->flash_reg = ioremap_nocache(csr_base, csr_len);
if (!denali->flash_reg) {
printk(KERN_ERR "Spectra: Unable to remap memory region\n");
ret = -ENOMEM;
goto failed_req_regions;
}
denali->flash_mem = ioremap_nocache(mem_base, mem_len);
if (!denali->flash_mem) {
printk(KERN_ERR "Spectra: ioremap_nocache failed!");
ret = -ENOMEM;
goto failed_remap_reg;
}
denali_hw_init(denali);
denali_drv_init(denali);
/* denali_isr register is done after all the hardware
* initilization is finished*/
if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
DENALI_NAND_NAME, denali)) {
printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
ret = -ENODEV;
goto failed_remap_mem;
}
/* now that our ISR is registered, we can enable interrupts */
denali_set_intr_modes(denali, true);
pci_set_drvdata(dev, denali);
denali->mtd.name = "denali-nand";
denali->mtd.owner = THIS_MODULE;
denali->mtd.priv = &denali->nand;
/* register the driver with the NAND core subsystem */
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.waitfunc = denali_waitfunc;
/* scan for NAND devices attached to the controller
* this is the first stage in a two step process to register
* with the nand subsystem */
if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto failed_req_irq;
}
/* MTD supported page sizes vary by kernel. We validate our
* kernel supports the device here.
*/
if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
ret = -ENODEV;
printk(KERN_ERR "Spectra: device size not supported by this "
"version of MTD.");
goto failed_req_irq;
}
/* support for multi nand
* MTD known nothing about multi nand,
* so we should tell it the real pagesize
* and anything necessery
*/
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
denali->nand.chipsize <<= (denali->devnum - 1);
denali->nand.page_shift += (denali->devnum - 1);
denali->nand.pagemask = (denali->nand.chipsize >>
denali->nand.page_shift) - 1;
denali->nand.bbt_erase_shift += (denali->devnum - 1);
denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
denali->nand.chip_shift += (denali->devnum - 1);
denali->mtd.writesize <<= (denali->devnum - 1);
denali->mtd.oobsize <<= (denali->devnum - 1);
denali->mtd.erasesize <<= (denali->devnum - 1);
denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
denali->bbtskipbytes *= denali->devnum;
/* second stage of the NAND scan
* this stage requires information regarding ECC and
* bad block management. */
/* Bad block management */
denali->nand.bbt_td = &bbt_main_descr;
denali->nand.bbt_md = &bbt_mirror_descr;
/* skip the scan for now until we have OOB read and write support */
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
denali->nand.options |= NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
/* Denali Controller only support 15bit and 8bit ECC in MRST,
* so just let controller do 15bit ECC for MLC and 8bit ECC for
* SLC if possible.
* */
if (denali->nand.cellinfo & 0xc &&
(denali->mtd.oobsize > (denali->bbtskipbytes +
ECC_15BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE)))) {
/* if MLC OOB size is large enough, use 15bit ECC*/
denali->nand.ecc.strength = 15;
denali->nand.ecc.layout = &nand_15bit_oob;
denali->nand.ecc.bytes = ECC_15BITS;
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
ECC_8BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE))) {
printk(KERN_ERR "Your NAND chip OOB is not large enough to"
" contain 8bit ECC correction codes");
goto failed_req_irq;
} else {
denali->nand.ecc.strength = 8;
denali->nand.ecc.layout = &nand_8bit_oob;
denali->nand.ecc.bytes = ECC_8BITS;
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
}
denali->nand.ecc.bytes *= denali->devnum;
denali->nand.ecc.strength *= denali->devnum;
denali->nand.ecc.layout->eccbytes *=
denali->mtd.writesize / ECC_SECTOR_SIZE;
denali->nand.ecc.layout->oobfree[0].offset =
denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
denali->nand.ecc.layout->oobfree[0].length =
denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
denali->bbtskipbytes;
/* Let driver know the total blocks number and
* how many blocks contained by each nand chip.
* blksperchip will help driver to know how many
* blocks is taken by FW.
* */
denali->totalblks = denali->mtd.size >>
denali->nand.phys_erase_shift;
denali->blksperchip = denali->totalblks / denali->nand.numchips;
/* These functions are required by the NAND core framework, otherwise,
* the NAND core will assert. However, we don't need them, so we'll stub
* them out. */
denali->nand.ecc.calculate = denali_ecc_calculate;
denali->nand.ecc.correct = denali_ecc_correct;
denali->nand.ecc.hwctl = denali_ecc_hwctl;
/* override the default read operations */
denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
denali->nand.ecc.write_page_raw = denali_write_page_raw;
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
denali->nand.erase_cmd = denali_erase;
if (nand_scan_tail(&denali->mtd)) {
ret = -ENXIO;
goto failed_req_irq;
}
ret = mtd_device_register(&denali->mtd, NULL, 0);
if (ret) {
dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
ret);
goto failed_req_irq;
}
return 0;
failed_req_irq:
denali_irq_cleanup(dev->irq, denali);
failed_remap_mem:
iounmap(denali->flash_mem);
failed_remap_reg:
iounmap(denali->flash_reg);
failed_req_regions:
pci_release_regions(dev);
failed_dma_map:
dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
DMA_BIDIRECTIONAL);
failed_enable_dev:
pci_disable_device(dev);
failed_alloc_memery:
kfree(denali);
return ret;
}
int denali_init(struct denali_nand_info *denali)
{
struct mtd_info *mtd = nand_to_mtd(&denali->nand);
int ret;
if (denali->platform == INTEL_CE4100) {
/*
* Due to a silicon limitation, we can only support
* ONFI timing mode 1 and below.
*/
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
return -EINVAL;
}
}
/* allocate a temporary buffer for nand_scan_ident() */
denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
GFP_DMA | GFP_KERNEL);
if (!denali->buf.buf)
return -ENOMEM;
mtd->dev.parent = denali->dev;
denali_hw_init(denali);
denali_drv_init(denali);
/* Request IRQ after all the hardware initialization is finished */
ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
IRQF_SHARED, DENALI_NAND_NAME, denali);
if (ret) {
dev_err(denali->dev, "Unable to request IRQ\n");
return ret;
}
/* now that our ISR is registered, we can enable interrupts */
denali_set_intr_modes(denali, true);
mtd->name = "denali-nand";
/* register the driver with the NAND core subsystem */
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.waitfunc = denali_waitfunc;
/*
* scan for NAND devices attached to the controller
* this is the first stage in a two step process to register
* with the nand subsystem
*/
ret = nand_scan_ident(mtd, denali->max_banks, NULL);
if (ret)
goto failed_req_irq;
/* allocate the right size buffer now */
devm_kfree(denali->dev, denali->buf.buf);
denali->buf.buf = devm_kzalloc(denali->dev,
mtd->writesize + mtd->oobsize,
GFP_KERNEL);
if (!denali->buf.buf) {
ret = -ENOMEM;
goto failed_req_irq;
}
/* Is 32-bit DMA supported? */
ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(denali->dev, "No usable DMA configuration\n");
goto failed_req_irq;
}
denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
mtd->writesize + mtd->oobsize,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
dev_err(denali->dev, "Failed to map DMA buffer\n");
ret = -EIO;
goto failed_req_irq;
}
/*
* support for multi nand
* MTD known nothing about multi nand, so we should tell it
* the real pagesize and anything necessery
*/
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
denali->nand.chipsize <<= denali->devnum - 1;
denali->nand.page_shift += denali->devnum - 1;
denali->nand.pagemask = (denali->nand.chipsize >>
denali->nand.page_shift) - 1;
denali->nand.bbt_erase_shift += denali->devnum - 1;
denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
denali->nand.chip_shift += denali->devnum - 1;
mtd->writesize <<= denali->devnum - 1;
mtd->oobsize <<= denali->devnum - 1;
mtd->erasesize <<= denali->devnum - 1;
mtd->size = denali->nand.numchips * denali->nand.chipsize;
denali->bbtskipbytes *= denali->devnum;
/*
* second stage of the NAND scan
* this stage requires information regarding ECC and
* bad block management.
*/
/* Bad block management */
denali->nand.bbt_td = &bbt_main_descr;
denali->nand.bbt_md = &bbt_mirror_descr;
/* skip the scan for now until we have OOB read and write support */
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
denali->nand.options |= NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
/* no subpage writes on denali */
denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
/*
* Denali Controller only support 15bit and 8bit ECC in MRST,
* so just let controller do 15bit ECC for MLC and 8bit ECC for
* SLC if possible.
* */
if (!nand_is_slc(&denali->nand) &&
(mtd->oobsize > (denali->bbtskipbytes +
ECC_15BITS * (mtd->writesize /
ECC_SECTOR_SIZE)))) {
/* if MLC OOB size is large enough, use 15bit ECC*/
denali->nand.ecc.strength = 15;
denali->nand.ecc.bytes = ECC_15BITS;
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
} else if (mtd->oobsize < (denali->bbtskipbytes +
ECC_8BITS * (mtd->writesize /
ECC_SECTOR_SIZE))) {
pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
goto failed_req_irq;
} else {
denali->nand.ecc.strength = 8;
denali->nand.ecc.bytes = ECC_8BITS;
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
}
mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
denali->nand.ecc.bytes *= denali->devnum;
denali->nand.ecc.strength *= denali->devnum;
/* override the default read operations */
denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
denali->nand.ecc.write_page_raw = denali_write_page_raw;
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
denali->nand.erase = denali_erase;
ret = nand_scan_tail(mtd);
if (ret)
goto failed_req_irq;
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
goto failed_req_irq;
}
return 0;
failed_req_irq:
denali_irq_cleanup(denali->irq, denali);
return ret;
}
/*
* Probe for the NAND device.
*/
static int __devinit plat_nand_probe(struct platform_device *pdev)
{
struct platform_nand_data *pdata = pdev->dev.platform_data;
struct plat_nand_data *data;
struct resource *res;
int err = 0;
if (pdata->chip.nr_chips < 1) {
dev_err(&pdev->dev, "invalid number of chips specified\n");
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENXIO;
/* Allocate memory for the device structure (and zero it) */
data = kzalloc(sizeof(struct plat_nand_data), GFP_KERNEL);
if (!data) {
dev_err(&pdev->dev, "failed to allocate device structure.\n");
return -ENOMEM;
}
if (!request_mem_region(res->start, resource_size(res),
dev_name(&pdev->dev))) {
dev_err(&pdev->dev, "request_mem_region failed\n");
err = -EBUSY;
goto out_free;
}
data->io_base = ioremap(res->start, resource_size(res));
if (data->io_base == NULL) {
dev_err(&pdev->dev, "ioremap failed\n");
err = -EIO;
goto out_release_io;
}
data->chip.priv = &data;
data->mtd.priv = &data->chip;
data->mtd.owner = THIS_MODULE;
data->mtd.name = dev_name(&pdev->dev);
data->chip.IO_ADDR_R = data->io_base;
data->chip.IO_ADDR_W = data->io_base;
data->chip.cmd_ctrl = pdata->ctrl.cmd_ctrl;
data->chip.dev_ready = pdata->ctrl.dev_ready;
data->chip.select_chip = pdata->ctrl.select_chip;
data->chip.write_buf = pdata->ctrl.write_buf;
data->chip.read_buf = pdata->ctrl.read_buf;
data->chip.chip_delay = pdata->chip.chip_delay;
data->chip.options |= pdata->chip.options;
data->chip.bbt_options |= pdata->chip.bbt_options;
data->chip.ecc.hwctl = pdata->ctrl.hwcontrol;
data->chip.ecc.layout = pdata->chip.ecclayout;
data->chip.ecc.mode = NAND_ECC_SOFT;
platform_set_drvdata(pdev, data);
/* Handle any platform specific setup */
if (pdata->ctrl.probe) {
err = pdata->ctrl.probe(pdev);
if (err)
goto out;
}
/* Scan to find existence of the device */
if (nand_scan_ident(&data->mtd, pdata->chip.nr_chips, NULL)) {
err = -ENXIO;
goto out;
}
if (pdata->chip.chip_fixup) {
err = pdata->chip.chip_fixup(&data->mtd);
if (err)
goto out;
}
if (nand_scan_tail(&data->mtd)) {
err = -ENXIO;
goto out;
}
err = mtd_device_parse_register(&data->mtd,
pdata->chip.part_probe_types, 0,
pdata->chip.partitions, pdata->chip.nr_partitions);
if (!err)
return err;
nand_release(&data->mtd);
out:
if (pdata->ctrl.remove)
pdata->ctrl.remove(pdev);
platform_set_drvdata(pdev, NULL);
iounmap(data->io_base);
out_release_io:
release_mem_region(res->start, resource_size(res));
out_free:
kfree(data);
return err;
}
int denali_init(struct denali_nand_info *denali)
{
int ret = 0;
uint32_t val;
if (denali->platform == INTEL_CE4100) {
/*
* Due to a silicon limitation, we can only support
* ONFI timing mode 1 and below.
*/
if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
return -EINVAL;
}
}
/* allocate a temporary buffer for nand_scan_ident() */
denali->buf.buf = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL);
if (!denali->buf.buf)
return -ENOMEM;
denali->mtd.parent = denali->dev;
denali_hw_init(denali);
denali_drv_init(denali);
denali_set_intr_modes(denali, true);
denali->mtd.name = "denali-nand";
denali->mtd.priv = &denali->nand;
/* register the driver with the NAND core subsystem */
denali->nand.read_buf = denali_read_buf;
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.waitfunc = denali_waitfunc;
/*
* scan for NAND devices attached to the controller
* this is the first stage in a two step process to register
* with the nand subsystem
*/
if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto failed_req_irq;
}
/* allocate the right size buffer now */
kfree(denali->buf.buf);
denali->buf.buf = kzalloc(denali->mtd.writesize + denali->mtd.oobsize,
GFP_KERNEL);
if (!denali->buf.buf) {
ret = -ENOMEM;
goto failed_req_irq;
}
/*
* support for multi nand
* MTD known nothing about multi nand, so we should tell it
* the real pagesize and anything necessery
*/
denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
denali->nand.chipsize <<= (denali->devnum - 1);
denali->nand.page_shift += (denali->devnum - 1);
denali->nand.pagemask = (denali->nand.chipsize >>
denali->nand.page_shift) - 1;
denali->nand.bbt_erase_shift += (denali->devnum - 1);
denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
denali->nand.chip_shift += (denali->devnum - 1);
denali->mtd.writesize <<= (denali->devnum - 1);
denali->mtd.oobsize <<= (denali->devnum - 1);
denali->mtd.erasesize <<= (denali->devnum - 1);
denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
denali->bbtskipbytes *= denali->devnum;
/*
* second stage of the NAND scan
* this stage requires information regarding ECC and
* bad block management.
*/
/* Bad block table description is set by nand framework,
see nand_bbt.c */
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
if (denali->have_hw_ecc_fixup) {
/* We have OOB support, so allow scan of BBT
and leave the OOB alone */
denali->nand.bbt_options |= NAND_BBT_NO_OOB;
} else {
/* skip the scan for now until we have OOB read and write support */
denali->nand.options |= NAND_SKIP_BBTSCAN;
}
/* no subpage writes on denali */
denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
/*
* Denali Controller only support 15bit and 8bit ECC in MRST,
* so just let controller do 15bit ECC for MLC and 8bit ECC for
* SLC if possible.
* */
if (!nand_is_slc(&denali->nand) &&
(denali->mtd.oobsize > (denali->bbtskipbytes +
ECC_15BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE)))) {
/* if MLC OOB size is large enough, use 15bit ECC*/
denali->nand.ecc.strength = 15;
denali->nand.ecc.layout = &nand_15bit_oob;
denali->nand.ecc.bytes = ECC_15BITS;
iowrite32(15, denali->flash_reg + ECC_CORRECTION);
} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
ECC_8BITS * (denali->mtd.writesize /
ECC_SECTOR_SIZE))) {
pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes");
goto failed_req_irq;
} else {
denali->nand.ecc.strength = 8;
denali->nand.ecc.layout = &nand_8bit_oob;
denali->nand.ecc.bytes = ECC_8BITS;
iowrite32(8, denali->flash_reg + ECC_CORRECTION);
}
denali->nand.ecc.bytes *= denali->devnum;
denali->nand.ecc.strength *= denali->devnum;
denali->nand.ecc.layout->eccbytes *=
denali->mtd.writesize / ECC_SECTOR_SIZE;
denali->nand.ecc.layout->oobfree[0].offset =
denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
denali->nand.ecc.layout->oobfree[0].length =
denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
denali->bbtskipbytes;
/*
* Let driver know the total blocks number and how many blocks
* contained by each nand chip. blksperchip will help driver to
* know how many blocks is taken by FW.
*/
denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift;
denali->blksperchip = denali->totalblks / denali->nand.numchips;
/* override the default read operations */
denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
denali->nand.ecc.write_page_raw = denali_write_page_raw;
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
/* Occasionally the controller is in SPARE or MAIN+SPARE
mode upon startup, and we want it to be MAIN only */
val = ioread32(denali->flash_reg + TRANSFER_MODE);
if (val != 0) {
int i;
dev_dbg(denali->dev,
"setting TRANSFER_MODE (%08x) back to MAIN only\n", val);
/* put all banks in MAIN mode, no SPARE */
iowrite32(0, denali->flash_reg + TRANSFER_SPARE_REG);
for (i = 0; i < 4; i++)
index_addr(denali, MODE_10 | BANK(i) | 1,
MAIN_ACCESS);
}
if (nand_scan_tail(&denali->mtd)) {
ret = -ENXIO;
goto failed_req_irq;
}
return add_mtd_nand_device(&denali->mtd, "nand");
failed_req_irq:
denali_irq_cleanup(denali->irq, denali);
return ret;
}
static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct arasan_nand_info *xnand;
struct mtd_info *mtd;
u8 maf_id, dev_id;
int err = -1;
u8 get_feature[4];
u8 set_feature[4] = {0x08, 0x00, 0x00, 0x00};
int ondie_ecc_enabled = 0;
u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
u32 i;
xnand = calloc(1, sizeof(struct arasan_nand_info));
if (!xnand) {
printf("%s: failed to allocate\n", __func__);
return -1;
}
xnand->nand_base = (void *)ARASAN_NAND_BASEADDR;
mtd = &nand_info[0];
nand_chip->priv = xnand;
mtd->priv = nand_chip;
/* Set address of NAND IO lines */
nand_chip->IO_ADDR_R = (void *)&arasan_nand_base->buf_dataport;
nand_chip->IO_ADDR_W = (void *)&arasan_nand_base->buf_dataport;
/* Set the driver entry points for MTD */
nand_chip->cmdfunc = arasan_nand_cmd_function;
nand_chip->select_chip = arasan_nand_select_chip;
nand_chip->read_byte = arasan_nand_read_byte;
/* Buffer read/write routines */
nand_chip->read_buf = arasan_nand_read_buf;
nand_chip->write_buf = arasan_nand_write_buf;
nand_chip->bbt_options = NAND_BBT_USE_FLASH;
writel(0x0, &arasan_nand_base->cmd_reg);
writel(0x0, &arasan_nand_base->pgm_reg);
/* first scan to find the device and get the page size */
if (nand_scan_ident(mtd, 1, NULL)) {
printf("%s: nand_scan_ident failed\n", __func__);
goto fail;
}
mtd->size = nand_chip->chipsize;
/* Send the command for reading device ID */
nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
/* Read manufacturer and device IDs */
maf_id = nand_chip->read_byte(mtd);
dev_id = nand_chip->read_byte(mtd);
if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
(dev_id == 0xa1) || (dev_id == 0xb1) ||
(dev_id == 0xaa) || (dev_id == 0xba) ||
(dev_id == 0xda) || (dev_id == 0xca) ||
(dev_id == 0xac) || (dev_id == 0xbc) ||
(dev_id == 0xdc) || (dev_id == 0xcc) ||
(dev_id == 0xa3) || (dev_id == 0xb3) ||
(dev_id == 0xd3) || (dev_id == 0xc3))) {
nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
ONDIE_ECC_FEATURE_ADDR, -1);
for (i = 0; i < 4; i++)
writeb(set_feature[i], nand_chip->IO_ADDR_W);
while (!(readl(&arasan_nand_base->intsts_reg) &
ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
timeout--;
}
if (!timeout) {
puts("ERROR:arasan_nand_init timedout:Xfer CMPLT\n");
goto fail;
}
writel(readl(&arasan_nand_base->intsts_enr) |
ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
&arasan_nand_base->intsts_enr);
writel(readl(&arasan_nand_base->intsts_reg) |
ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
&arasan_nand_base->intsts_reg);
nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
ONDIE_ECC_FEATURE_ADDR, -1);
for (i = 0; i < 4; i++)
get_feature[i] = nand_chip->read_byte(mtd);
if (get_feature[0] & 0x08) {
debug("%s: OnDie ECC flash\n", __func__);
ondie_ecc_enabled = 1;
} else {
printf("%s: Unable to detect OnDie ECC\n", __func__);
}
}
if (!ondie_ecc_enabled) {
nand_chip->ecc.mode = NAND_ECC_HW;
nand_chip->ecc.strength = 1;
nand_chip->ecc.hwctl = NULL;
nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
nand_chip->ecc.read_oob = arasan_nand_read_oob;
nand_chip->ecc.write_oob = arasan_nand_write_oob;
}
arasan_nand_ecc_init(mtd);
if (nand_scan_tail(mtd)) {
printf("%s: nand_scan_tailfailed\n", __func__);
goto fail;
}
if (nand_register(devnum)) {
printf("Nand Register Fail\n");
goto fail;
}
return 0;
fail:
kfree(xnand);
return err;
}
int denali_init(struct denali_nand_info *denali)
{
struct mtd_info *mtd = nand_to_mtd(&denali->nand);
int ret;
denali_hw_init(denali);
mtd->name = "denali-nand";
mtd->owner = THIS_MODULE;
/* register the driver with the NAND core subsystem */
denali->nand.select_chip = denali_select_chip;
denali->nand.cmdfunc = denali_cmdfunc;
denali->nand.read_byte = denali_read_byte;
denali->nand.read_buf = denali_read_buf;
denali->nand.waitfunc = denali_waitfunc;
/*
* scan for NAND devices attached to the controller
* this is the first stage in a two step process to register
* with the nand subsystem
*/
if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
ret = -ENXIO;
goto fail;
}
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
/* check whether flash got BBT table (located at end of flash). As we
* use NAND_BBT_NO_OOB, the BBT page will start with
* bbt_pattern. We will have mirror pattern too */
denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
/*
* We are using main + spare with ECC support. As BBT need ECC support,
* we need to ensure BBT code don't write to OOB for the BBT pattern.
* All BBT info will be stored into data area with ECC support.
*/
denali->nand.bbt_options |= NAND_BBT_NO_OOB;
#endif
denali->nand.ecc.mode = NAND_ECC_HW;
denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
/* no subpage writes on denali */
denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
/*
* Tell driver the ecc strength. This register may be already set
* correctly. So we read this value out.
*/
denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
switch (denali->nand.ecc.size) {
case 512:
denali->nand.ecc.bytes =
(denali->nand.ecc.strength * 13 + 15) / 16 * 2;
break;
case 1024:
denali->nand.ecc.bytes =
(denali->nand.ecc.strength * 14 + 15) / 16 * 2;
break;
default:
pr_err("Unsupported ECC size\n");
ret = -EINVAL;
goto fail;
}
nand_oob.eccbytes = denali->nand.ecc.bytes;
denali->nand.ecc.layout = &nand_oob;
writel(mtd->erasesize / mtd->writesize,
denali->flash_reg + PAGES_PER_BLOCK);
writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
denali->flash_reg + DEVICE_WIDTH);
writel(mtd->writesize,
denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
writel(mtd->oobsize,
denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
writel(1, denali->flash_reg + DEVICES_CONNECTED);
/* override the default operations */
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
denali->nand.ecc.write_page_raw = denali_write_page_raw;
denali->nand.ecc.read_oob = denali_read_oob;
denali->nand.ecc.write_oob = denali_write_oob;
if (nand_scan_tail(mtd)) {
ret = -ENXIO;
goto fail;
}
ret = nand_register(0, mtd);
fail:
return ret;
}
