static int __init nlm_uart_init(void)
{
nlm_reg_t *mmio;
mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
xlr_uart_data[0].membase = (void __iomem *)mmio;
xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
xlr_uart_data[1].membase = (void __iomem *)mmio;
xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
return platform_device_register(&uart_device);
}
static void nlm_linux_exit(void)
{
nlm_reg_t *mmio;
mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
/* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
for ( ; ; )
cpu_wait();
}
int nlm_get_pci_mode()
{
nlm_reg_t *pcix_ctrl_mmio;
uint32_t mode;
if (is_xls()) {
return XLR_PCI_HOST_MODE;
}
pcix_ctrl_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
mode = pcix_ctrl_mmio[PCIX_HOST_MODE_CTRL_STATUS_REG];
if(mode & 0x2){
return XLR_PCI_HOST_MODE;
}
return XLR_PCI_DEV_MODE;
}
static void nlm_early_serial_setup(void)
{
struct uart_port s;
nlm_reg_t *uart_base;
uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
memset(&s, 0, sizeof(s));
s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
s.iotype = UPIO_MEM32;
s.regshift = 2;
s.irq = PIC_UART_0_IRQ;
s.uartclk = PIC_CLKS_PER_SEC;
s.serial_in = nlm_xlr_uart_in;
s.serial_out = nlm_xlr_uart_out;
s.mapbase = (unsigned long)uart_base;
s.membase = (unsigned char __iomem *)uart_base;
early_serial_setup(&s);
}
