int altera_ci_tuner_reset(void *dev, int ci_nr)
{
struct fpga_inode *temp_int = find_inode(dev);
struct fpga_internal *inter = NULL;
u8 store;
ci_dbg_print("%s\n", __func__);
if (temp_int == NULL)
return -1;
if (temp_int->internal == NULL)
return -1;
inter = temp_int->internal;
mutex_lock(&inter->fpga_mutex);
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
store &= ~(4 << (2 - ci_nr));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
msleep(100);
store |= (4 << (2 - ci_nr));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
mutex_unlock(&inter->fpga_mutex);
return 0;
}
static void altera_toggle_fullts_streaming(struct netup_hw_pid_filter *pid_filt,
int filt_nr, int onoff)
{
struct fpga_internal *inter = pid_filt->internal;
u8 store = 0;
int i;
pid_dbg_print("%s: pid_filt->nr[%d] now %s\n", __func__, pid_filt->nr,
onoff ? "off" : "on");
if (onoff)/* 0 - on, 1 - off */
store = 0xff;/* ignore pid */
else
store = 0;/* enable pid */
mutex_lock(&inter->fpga_mutex);
for (i = 0; i < 1024; i++) {
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
((i >> 8) & 0x03) | (pid_filt->nr << 2), 0);
/* pid 0-0x1f always enabled */
netup_fpga_op_rw(inter, NETUP_CI_PID_DATA,
(i > 3 ? store : 0), 0);
}
mutex_unlock(&inter->fpga_mutex);
}
static void altera_pid_control(struct netup_hw_pid_filter *pid_filt,
u16 pid, int onoff)
{
struct fpga_internal *inter = pid_filt->internal;
u8 store = 0;
/* pid 0-0x1f always enabled, don't touch them */
if ((pid == 0x2000) || (pid < 0x20))
return;
mutex_lock(&inter->fpga_mutex);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0);
netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
((pid >> 11) & 0x03) | (pid_filt->nr << 2), 0);
store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD);
if (onoff)/* 0 - on, 1 - off */
store |= (1 << (pid & 7));
else
store &= ~(1 << (pid & 7));
netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0);
mutex_unlock(&inter->fpga_mutex);
pid_dbg_print("%s: (%d) set pid: %5d 0x%04x '%s'\n", __func__,
pid_filt->nr, pid, pid, onoff ? "off" : "on");
}
/* work handler */
static void netup_read_ci_status(struct work_struct *work)
{
struct fpga_internal *inter =
container_of(work, struct fpga_internal, work);
int ret;
ci_dbg_print("%s\n", __func__);
mutex_lock(&inter->fpga_mutex);
/* ack' irq */
ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
mutex_unlock(&inter->fpga_mutex);
if (inter->state[1] != NULL) {
inter->state[1]->status =
((ret & 1) == 0 ?
DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY : 0);
ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
__func__, inter->state[1]->status);
};
if (inter->state[0] != NULL) {
inter->state[0]->status =
((ret & 2) == 0 ?
DVB_CA_EN50221_POLL_CAM_PRESENT |
DVB_CA_EN50221_POLL_CAM_READY : 0);
ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
__func__, inter->state[0]->status);
};
}
/* flag - mem/io, read - read/write */
int altera_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
u8 flag, u8 read, int addr, u8 val)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
u8 store;
int mem = 0;
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0);
netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0);
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
store &= 0x0f;
store |= ((state->nr << 7) | (flag << 6));
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0);
mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read);
mutex_unlock(&inter->fpga_mutex);
ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__,
(read) ? "read" : "write", addr,
(flag == NETUP_CI_FLG_CTL) ? "ctl" : "mem",
(read) ? mem : val);
return mem;
}
static int altera_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
/* reasonable timeout for CI reset is 10 seconds */
unsigned long t_out = jiffies + msecs_to_jiffies(9999);
int ret;
ci_dbg_print("%s\n", __func__);
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
(ret & 0xcf) | (1 << (5 - state->nr)), 0);
mutex_unlock(&inter->fpga_mutex);
for (;;) {
mdelay(50);
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
0, NETUP_CI_FLG_RD);
mutex_unlock(&inter->fpga_mutex);
if ((ret & (1 << (5 - state->nr))) == 0)
break;
if (time_after(jiffies, t_out))
break;
}
ci_dbg_print("%s: %d msecs\n", __func__,
jiffies_to_msecs(jiffies + msecs_to_jiffies(9999) - t_out));
return 0;
}
int altera_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
{
struct altera_ci_state *state = en50221->data;
struct fpga_internal *inter = state->internal;
int ret;
ci_dbg_print("%s\n", __func__);
if (0 != slot)
return -EINVAL;
mutex_lock(&inter->fpga_mutex);
ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
(ret & 0x0f) | (1 << (3 - state->nr)), 0);
mutex_unlock(&inter->fpga_mutex);
return 0;
}
int altera_ci_init(struct altera_ci_config *config, int ci_nr)
{
struct altera_ci_state *state;
struct fpga_inode *temp_int = find_inode(config->dev);
struct fpga_internal *inter = NULL;
int ret = 0;
u8 store = 0;
state = kzalloc(sizeof(struct altera_ci_state), GFP_KERNEL);
ci_dbg_print("%s\n", __func__);
if (!state) {
ret = -ENOMEM;
goto err;
}
if (temp_int != NULL) {
inter = temp_int->internal;
(inter->cis_used)++;
ci_dbg_print("%s: Find Internal Structure!\n", __func__);
} else {
inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
if (!inter) {
ret = -ENOMEM;
goto err;
}
temp_int = append_internal(inter);
inter->cis_used = 1;
inter->dev = config->dev;
inter->fpga_rw = config->fpga_rw;
mutex_init(&inter->fpga_mutex);
inter->strt_wrk = 1;
ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
}
ci_dbg_print("%s: setting state = %p for ci = %d\n", __func__,
state, ci_nr - 1);
inter->state[ci_nr - 1] = state;
state->internal = inter;
state->nr = ci_nr - 1;
state->ca.owner = THIS_MODULE;
state->ca.read_attribute_mem = altera_ci_read_attribute_mem;
state->ca.write_attribute_mem = altera_ci_write_attribute_mem;
state->ca.read_cam_control = altera_ci_read_cam_ctl;
state->ca.write_cam_control = altera_ci_write_cam_ctl;
state->ca.slot_reset = altera_ci_slot_reset;
state->ca.slot_shutdown = altera_ci_slot_shutdown;
state->ca.slot_ts_enable = altera_ci_slot_ts_ctl;
state->ca.poll_slot_status = altera_poll_ci_slot_status;
state->ca.data = state;
ret = dvb_ca_en50221_init(config->adapter,
&state->ca,
/* flags */ 0,
/* n_slots */ 1);
if (0 != ret)
goto err;
altera_hw_filt_init(config, ci_nr);
if (inter->strt_wrk) {
INIT_WORK(&inter->work, netup_read_ci_status);
inter->strt_wrk = 0;
}
ci_dbg_print("%s: CI initialized!\n", __func__);
mutex_lock(&inter->fpga_mutex);
/* Enable div */
netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0);
netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0);
/* enable TS out */
store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
store |= (3 << 4);
netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD);
/* enable irq */
netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0);
mutex_unlock(&inter->fpga_mutex);
ci_dbg_print("%s: NetUP CI Revision = 0x%x\n", __func__, ret);
schedule_work(&inter->work);
return 0;
err:
ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
kfree(state);
return ret;
}
