void Operator::outputVHDL(std::ostream& o, std::string name) {
if(isSequential() && getClkName().compare("") == 0) {
std::cerr << "-- Can't find clock port for sequential component." << std::endl;
}
licence(o);
stdLibs(o);
outputVHDLEntity(o);
newArchitecture(o,name);
o << buildVHDLComponentDeclarations();
o << buildVHDLSignalDeclarations();
beginArchitecture(o);
o<<buildVHDLRegisters();
o << vhdl.str();
endArchitecture(o);
}
void LNSSqrt::outputVHDL(std::ostream& o, std::string name)
{
licence(o,"Jérémie Detrey, Florent de Dinechin (2003-2004), Sylvain Collange (2008)");
Operator::stdLibs(o);
outputVHDLEntity(o);
newArchitecture(o,name);
o
<< tab << "constant wE : positive := " << wE <<";\n"
<< tab << "constant wF : positive := " << wF <<";\n"
<< tab << "\n"
<< tab << "signal sRn : std_logic;\n"
<< tab << "signal eRn : std_logic_vector(wE+wF-1 downto 0);\n"
<< tab << "signal xRn : std_logic_vector(1 downto 0);\n"
<< tab << "signal nRn : std_logic_vector(wE+wF+2 downto 0);\n"
<< tab << "signal nRx : std_logic_vector(wE+wF+2 downto 0);\n"
<< tab << "\n"
<< tab << "signal xsA : std_logic_vector(2 downto 0);\n";
beginArchitecture(o);
o
<< tab << "eRn <= nA(wE+wF-1) & nA(wE+wF-1 downto 1);\n"
<< tab << "\n"
<< tab << "sRn <= nA(wE+wF);\n"
<< tab << "xRn <= \"01\";\n"
<< tab << "nRn <= xRn & sRn & eRn;\n"
<< tab << "\n"
<< tab << "xsA <= nA(wE+wF+2 downto wE+wF);\n"
<< tab << "\n"
<< tab << "with xsA select\n"
<< tab << "nR(wE+wF+2 downto wE+wF+1) <= xsA(2 downto 1) when \"001\" | \"000\" | \"010\" | \"100\",\n"
<< tab << " \"11\" when others;\n"
<< tab << "\n"
<< tab << "nR(wE+wF downto 0) <= nRn(wE+wF downto 0);\n"
<< "end architecture;\n";
}
