static void apply_config(nrfx_uart_t const * p_instance,
nrfx_uart_config_t const * p_config)
{
if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_pin_set(p_config->pseltxd);
nrf_gpio_cfg_output(p_config->pseltxd);
}
if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL);
}
nrf_uart_baudrate_set(p_instance->p_reg, p_config->baudrate);
nrf_uart_configure(p_instance->p_reg, p_config->parity, p_config->hwfc);
nrf_uart_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd);
if (p_config->hwfc == NRF_UART_HWFC_ENABLED)
{
if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
}
if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED)
{
nrf_gpio_pin_set(p_config->pselrts);
nrf_gpio_cfg_output(p_config->pselrts);
}
nrf_uart_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts);
}
}
otError otPlatUartEnable(void)
{
otError error = OT_ERROR_NONE;
otEXPECT_ACTION(sUartEnabled == false, error = OT_ERROR_ALREADY);
// Set up TX and RX pins.
nrf_gpio_pin_set(UART_PIN_TX);
nrf_gpio_cfg_output(UART_PIN_TX);
nrf_gpio_cfg_input(UART_PIN_RX, NRF_GPIO_PIN_NOPULL);
nrf_uart_txrx_pins_set(UART_INSTANCE, UART_PIN_TX, UART_PIN_RX);
#if (UART_HWFC == NRF_UART_HWFC_ENABLED)
// Set up CTS and RTS pins.
nrf_gpio_cfg_input(UART_PIN_CTS, NRF_GPIO_PIN_NOPULL);
nrf_gpio_pin_set(UART_PIN_RTS);
nrf_gpio_cfg_output(UART_PIN_RTS);
nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_PIN_RTS, UART_PIN_CTS);
#endif
// Configure baudrate.
nrf_uart_baudrate_set(UART_INSTANCE, UART_BAUDRATE);
// Configure parity and hardware flow control.
nrf_uart_configure(UART_INSTANCE, UART_PARITY, UART_HWFC);
// Clear UART specific events.
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR);
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
// Enable interrupts for TX.
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
// Enable interrupts for RX.
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
// Configure NVIC to handle UART interrupts.
NVIC_SetPriority(UART_IRQN, UART_IRQ_PRIORITY);
NVIC_ClearPendingIRQ(UART_IRQN);
NVIC_EnableIRQ(UART_IRQN);
// Start HFCLK
nrf_drv_clock_hfclk_request(NULL);
while (!nrf_drv_clock_hfclk_is_running())
{
}
// Enable UART instance, and start RX on it.
nrf_uart_enable(UART_INSTANCE);
nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX);
sUartEnabled = true;
exit:
return error;
}
void nrf5UartInit(void)
{
// Set up TX and RX pins.
nrf_gpio_pin_set(UART_PIN_TX);
nrf_gpio_cfg_output(UART_PIN_TX);
nrf_gpio_cfg_input(UART_PIN_RX, NRF_GPIO_PIN_NOPULL);
nrf_uart_txrx_pins_set(UART_INSTANCE, UART_PIN_TX, UART_PIN_RX);
#if (UART_HWFC == NRF_UART_HWFC_ENABLED)
// Set up CTS and RTS pins.
nrf_gpio_cfg_input(UART_PIN_CTS, NRF_GPIO_PIN_NOPULL);
nrf_gpio_pin_set(UART_PIN_RTS);
nrf_gpio_cfg_output(UART_PIN_RTS);
nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_PIN_RTS, UART_PIN_CTS);
#endif
// Configure baudrate.
nrf_uart_baudrate_set(UART_INSTANCE, UART_BAUDRATE);
// Configure parity and hardware flow control.
nrf_uart_configure(UART_INSTANCE, UART_PARITY, UART_HWFC);
// Clear UART specific events.
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR);
nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
// Enable interrupts for TX.
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
// Enable interrupts for RX.
nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_ERROR);
// Configure NVIC to handle UART interrupts.
NVIC_SetPriority(UART_IRQN, UART_IRQ_PRIORITY);
NVIC_ClearPendingIRQ(UART_IRQN);
NVIC_EnableIRQ(UART_IRQN);
}
/**
* @brief Initialize UART channel
*
* This routine is called to reset the chip in a quiescent state.
* It is assumed that this function is called only once per UART.
*
* @param dev UART device struct
*
* @return 0 on success
*/
static int uart_nrfx_init(struct device *dev)
{
struct device *gpio_dev;
int err;
gpio_dev = device_get_binding(CONFIG_GPIO_NRF5_P0_DEV_NAME);
__ASSERT(gpio_dev,
"UART init failed. Cannot find %s",
CONFIG_GPIO_NRF5_P0_DEV_NAME);
/* Setting default height state of the TX PIN to avoid glitches
* on the line during peripheral activation/deactivation.
*/
gpio_pin_write(gpio_dev, CONFIG_UART_0_NRF_TX_PIN, 1);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_TX_PIN,
GPIO_DIR_OUT);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_RX_PIN,
GPIO_DIR_IN);
nrf_uart_txrx_pins_set(NRF_UART0,
CONFIG_UART_0_NRF_TX_PIN,
CONFIG_UART_0_NRF_RX_PIN);
#ifdef CONFIG_UART_0_NRF_FLOW_CONTROL
/* Setting default height state of the RTS PIN to avoid glitches
* on the line during peripheral activation/deactivation.
*/
gpio_pin_write(gpio_dev, CONFIG_UART_0_NRF_RTS_PIN, 1);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_RTS_PIN,
GPIO_DIR_OUT);
gpio_pin_configure(gpio_dev,
CONFIG_UART_0_NRF_CTS_PIN,
GPIO_DIR_IN);
nrf_uart_hwfc_pins_set(NRF_UART0,
CONFIG_UART_0_NRF_RTS_PIN,
CONFIG_UART_0_NRF_CTS_PIN);
#endif /* CONFIG_UART_0_NRF_FLOW_CONTROL */
nrf_uart_configure(NRF_UART0,
#ifdef CONFIG_UART_0_NRF_PARITY_BIT
NRF_UART_PARITY_INCLUDED,
#else
NRF_UART_PARITY_EXCLUDED,
#endif /* CONFIG_UART_0_NRF_PARITY_BIT */
#ifdef CONFIG_UART_0_NRF_FLOW_CONTROL
NRF_UART_HWFC_ENABLED);
#else
NRF_UART_HWFC_DISABLED);
#endif /* CONFIG_UART_0_NRF_PARITY_BIT */
/* Set baud rate */
err = baudrate_set(dev, CONFIG_UART_0_BAUD_RATE);
if (err) {
return err;
}
/* Enable receiver and transmitter */
nrf_uart_enable(NRF_UART0);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(NRF_UART0, NRF_UART_EVENT_RXDRDY);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTTX);
nrf_uart_task_trigger(NRF_UART0, NRF_UART_TASK_STARTRX);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
IRQ_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_UART0),
CONFIG_UART_0_IRQ_PRI,
uart_nrfx_isr,
DEVICE_GET(uart_nrfx_uart0),
0);
irq_enable(NRFX_IRQ_NUMBER_GET(NRF_UART0));
#endif
return 0;
}
static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
{
nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG;
UART_CFG_T *instance = &uart0;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
instance = (UART_CFG_T*)serial->parent.user_data;
}
nrf_uart_disable(instance->uart.reg.p_uart);
switch (cfg->baud_rate)
{
case 115200:
config.baudrate = NRF_UART_BAUDRATE_115200;
break;
case 9600:
config.baudrate = NRF_UART_BAUDRATE_9600;
break;
default:
config.baudrate = NRF_UART_BAUDRATE_115200;
break;
}
if (cfg->parity == PARITY_NONE)
{
config.parity = NRF_UART_PARITY_EXCLUDED;
}
else
{
config.parity = NRF_UART_PARITY_INCLUDED;
}
config.hwfc = NRF_UART_HWFC_DISABLED;
config.interrupt_priority = APP_IRQ_PRIORITY_LOWEST;
config.pselcts = 0;
config.pselrts = 0;
config.pselrxd = instance->rx_pin;
config.pseltxd = instance->tx_pin;
nrf_gpio_pin_set(config.pseltxd);
nrf_gpio_cfg_output(config.pseltxd);
nrf_gpio_pin_clear(config.pseltxd);
nrf_gpio_cfg_input(config.pselrxd, NRF_GPIO_PIN_NOPULL);
nrf_uart_baudrate_set(instance->uart.reg.p_uart, config.baudrate);
nrf_uart_configure(instance->uart.reg.p_uart, config.parity, config.hwfc);
nrf_uart_txrx_pins_set(instance->uart.reg.p_uart, config.pseltxd, config.pselrxd);
if (config.hwfc == NRF_UART_HWFC_ENABLED)
{
nrf_uart_hwfc_pins_set(instance->uart.reg.p_uart, config.pselrts, config.pselcts);
}
nrf_uart_event_clear(instance->uart.reg.p_uart, NRF_UART_EVENT_TXDRDY);
nrf_uart_event_clear(instance->uart.reg.p_uart, NRF_UART_EVENT_RXDRDY);
nrf_uart_event_clear(instance->uart.reg.p_uart, NRF_UART_EVENT_RXTO);
nrf_uart_event_clear(instance->uart.reg.p_uart, NRF_UART_EVENT_ERROR);
nrf_uart_int_enable(instance->uart.reg.p_uart, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR);
nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)instance->uart.reg.p_uart), config.interrupt_priority);
nrf_uart_enable(instance->uart.reg.p_uart);
// nrf_uart_task_trigger(instance->uart.reg.p_uart, NRF_UART_TASK_STARTRX);
working_cfg = instance;
return RT_EOK;
}
