Пример #1
0
int
nouveau_fb_created(struct nouveau_fb *pfb)
{
	static const char *name[] = {
		[NV_MEM_TYPE_UNKNOWN] = "unknown",
		[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
		[NV_MEM_TYPE_SGRAM  ] = "SGRAM",
		[NV_MEM_TYPE_SDRAM  ] = "SDRAM",
		[NV_MEM_TYPE_DDR1   ] = "DDR1",
		[NV_MEM_TYPE_DDR2   ] = "DDR2",
		[NV_MEM_TYPE_DDR3   ] = "DDR3",
		[NV_MEM_TYPE_GDDR2  ] = "GDDR2",
		[NV_MEM_TYPE_GDDR3  ] = "GDDR3",
		[NV_MEM_TYPE_GDDR4  ] = "GDDR4",
		[NV_MEM_TYPE_GDDR5  ] = "GDDR5",
	};

	if (pfb->ram.size == 0) {
		nv_fatal(pfb, "no vram detected!!\n");
		return -ERANGE;
	}

	nv_info(pfb, "RAM type: %s\n", name[pfb->ram.type]);
	nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram.size >> 20));
	return 0;
}
Пример #2
0
int
nouveau_fb_preinit(struct nouveau_fb *pfb)
{
	static const char *name[] = {
		[NV_MEM_TYPE_UNKNOWN] = "unknown",
		[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
		[NV_MEM_TYPE_SGRAM  ] = "SGRAM",
		[NV_MEM_TYPE_SDRAM  ] = "SDRAM",
		[NV_MEM_TYPE_DDR1   ] = "DDR1",
		[NV_MEM_TYPE_DDR2   ] = "DDR2",
		[NV_MEM_TYPE_DDR3   ] = "DDR3",
		[NV_MEM_TYPE_GDDR2  ] = "GDDR2",
		[NV_MEM_TYPE_GDDR3  ] = "GDDR3",
		[NV_MEM_TYPE_GDDR4  ] = "GDDR4",
		[NV_MEM_TYPE_GDDR5  ] = "GDDR5",
	};
	int ret, tags;

	tags = pfb->ram.init(pfb);
	if (tags < 0 || !pfb->ram.size) {
		nv_fatal(pfb, "error detecting memory configuration!!\n");
		return (tags < 0) ? tags : -ERANGE;
	}

	if (!nouveau_mm_initialised(&pfb->vram)) {
		ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram.size >> 12, 1);
		if (ret)
			return ret;
	}
Пример #3
0
bool gm100_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
        case 0x117:
            device->cname = "GM107";
            break;

        case 0x120:
            device->cname = "GM200"; // Titan X
            break;

        case 0x124:
            device->cname = "GM204"; // GTX 980
            break;

        case 0x126:
            device->cname = "GM206"; // GTX 960
            break;

        default:
            nv_fatal(device, "unknown Maxwell chipset 0x%x\n", device->chipset);
            return false;
	}

	return true;
}
Пример #4
0
bool GeforceSensors::startupCheck(IOService *provider)
{
    HWSensorsDebugLog("Initializing...");

    struct nouveau_device *device = &card;

    if ((card.card_index = takeVacantGPUIndex()) < 0) {
        nv_fatal(device, "failed to take vacant GPU index\n");
        return false;
    }

    // map device memory
    if ((device->pcidev = pciDevice)) {

        device->pcidev->setMemoryEnable(true);

        if ((device->mmio = device->pcidev->mapDeviceMemoryWithIndex(0))) {
            nv_debug(device, "memory mapped successfully\n");
        }
        else {
            nv_fatal(device, "failed to map memory\n");
            return false;
        }
    }
    else {
        HWSensorsFatalLog("(pci%d): [Fatal] failed to assign PCI device", pciDevice->getBusNumber());
        return false;
    }

    // identify chipset
    if (!nouveau_identify(device)) {
        return false;
    }

    if (!shadowBios()) {
        nv_error(device, "early VBIOS shadow failed, will try after accelerator started\n");
    }

    return true;
}
Пример #5
0
int
gm100_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x117:
		device->cname = "GM107";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
#if 0
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
#endif
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm107_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] =  gm107_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
#if 0
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nv108_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
#endif
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
#endif
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
#endif
		break;
	default:
		nv_fatal(device, "unknown Maxwell chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #6
0
int
nv04_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x04:
		device->cname = "NV04";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv04_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x05:
		device->cname = "NV05";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv05_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv04_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv04_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv04_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown RIVA chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #7
0
int
nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, int length, void **pobject)
{
	struct nouveau_fb_impl *impl = (void *)oclass;
	static const char *name[] = {
		[NV_MEM_TYPE_UNKNOWN] = "unknown",
		[NV_MEM_TYPE_STOLEN ] = "stolen system memory",
		[NV_MEM_TYPE_SGRAM  ] = "SGRAM",
		[NV_MEM_TYPE_SDRAM  ] = "SDRAM",
		[NV_MEM_TYPE_DDR1   ] = "DDR1",
		[NV_MEM_TYPE_DDR2   ] = "DDR2",
		[NV_MEM_TYPE_DDR3   ] = "DDR3",
		[NV_MEM_TYPE_GDDR2  ] = "GDDR2",
		[NV_MEM_TYPE_GDDR3  ] = "GDDR3",
		[NV_MEM_TYPE_GDDR4  ] = "GDDR4",
		[NV_MEM_TYPE_GDDR5  ] = "GDDR5",
	};
	struct nouveau_object *ram;
	struct nouveau_fb *pfb;
	int ret;

	ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
				     length, pobject);
	pfb = *pobject;
	if (ret)
		return ret;

	pfb->memtype_valid = impl->memtype;

	ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb),
				  impl->ram, NULL, 0, &ram);
	if (ret) {
		nv_fatal(pfb, "error detecting memory configuration!!\n");
		return ret;
	}

	atomic_dec(&ram->parent->refcount);
	atomic_dec(&ram->engine->refcount);
	pfb->ram = (void *)ram;

	if (!nouveau_mm_initialised(&pfb->vram)) {
		ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
		if (ret)
			return ret;
	}
Пример #8
0
bool nve0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
        case 0xe4:
            device->cname = "GK104";
            break;
        case 0xe6:
            device->cname = "GK106";
            break;
        case 0xe7:
            device->cname = "GK107";
            break;
        default:
            nv_fatal(device, "unknown Kepler chipset\n");
            return false;
	}
    
	return true;
}
Пример #9
0
int
nv20_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x20:
		device->cname = "NV20";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x25:
		device->cname = "NV25";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x28:
		device->cname = "NV28";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x2a:
		device->cname = "NV2A";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Kelvin chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #10
0
int
nv30_identify(struct nvkm_device *device)
{
    switch (device->chipset) {
    case 0x30:
        device->cname = "NV30";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
        break;
    case 0x35:
        device->cname = "NV35";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] =  nv35_fb_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
        break;
    case 0x31:
        device->cname = "NV31";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] =  nv30_fb_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
        device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
        break;
    case 0x36:
        device->cname = "NV36";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] =  nv36_fb_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
        device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
        break;
    case 0x34:
        device->cname = "NV34";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv10_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] =  nv10_fb_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
        device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
        break;
    default:
        nv_fatal(device, "unknown Rankine chipset\n");
        return -EINVAL;
    }

    return 0;
}
Пример #11
0
bool GeforceSensors::managedStart(IOService *provider)
{
    HWSensorsDebugLog("Starting...");

    struct nouveau_device *device = &card;

    if (!device->bios.data || !device->bios.size) {
        if (!shadowBios()) {
            nv_fatal(device, "unable to shadow VBIOS\n");
            releaseGPUIndex(card.card_index);
            card.card_index = -1;
            return false;
        }
    }

    nouveau_vbios_init(device);
    nouveau_bios_parse(device);
    
    // initialize funcs and variables
    if (!nouveau_init(device)) {
        nv_error(device, "unable to initialize monitoring driver\n");
        releaseGPUIndex(card.card_index);
        card.card_index = -1;
        return false;
    }
    
    nv_info(device, "chipset: %s (NV%02X) bios: %02x.%02x.%02x.%02x\n", device->cname, device->chipset, device->bios.version.major, device->bios.version.chip, device->bios.version.minor, device->bios.version.micro);
    
    if (device->card_type < NV_C0) {
        // init i2c structures
        nouveau_i2c_create(device);
        
        // setup nouveau i2c sensors
        nouveau_i2c_probe(device);
    }
    
    // Register sensors
    char key[5];

    if (card.core_temp_get || card.board_temp_get) {
        nv_debug(device, "registering i2c temperature sensors...\n");
        
        if (card.core_temp_get) {
            snprintf(key, 5, KEY_FORMAT_GPU_DIODE_TEMPERATURE, card.card_index);
            addSensorForKey(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_core);
        }
        else if (card.board_temp_get) {
            snprintf(key, 5, KEY_FORMAT_GPU_HEATSINK_TEMPERATURE, card.card_index);
            addSensorForKey(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_board);
        }
    }
    else if (card.temp_get)
    {
        nv_debug(device, "registering temperature sensors...\n");
        
        snprintf(key, 5, KEY_FORMAT_GPU_DIODE_TEMPERATURE, card.card_index);
        addSensorForKey(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_diode);
    }
    
    int arg_value = 1;
    
    if (card.clocks_get && !PE_parse_boot_argn("-gpusensors-no-clocks", &arg_value, sizeof(arg_value))) {
        nv_debug(device, "registering clocks sensors...\n");
        
        if (card.clocks_get(&card, nouveau_clock_core) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_FREQUENCY, card.card_index);
            addSensorForKey(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_core);
        }
        
        //        if (card.clocks_get(&card, nouveau_clock_shader) > 0) {
        //            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_SHADER_FREQUENCY, card.card_index);
        //            addSensor(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_shader);
        //        }
        
        if (card.clocks_get(&card, nouveau_clock_rop) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_ROP_FREQUENCY, card.card_index);
            addSensorForKey(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_rop);
        }
        
        if (card.clocks_get(&card, nouveau_clock_memory) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_MEMORY_FREQUENCY, card.card_index);
            addSensorForKey(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_memory);
        }
    }
    
    if (card.fan_pwm_get || card.fan_rpm_get) {
        nv_debug(device, "registering PWM sensors...\n");
        
        char title[DIAG_FUNCTION_STR_LEN];
        snprintf (title, DIAG_FUNCTION_STR_LEN, "GPU %X", card.card_index + 1);
        
        if (card.fan_rpm_get && card.fan_rpm_get(&card) >= 0)
            addTachometer(nouveau_fan_rpm, title, GPU_FAN_RPM, card.card_index);
        
        if (card.fan_pwm_get && card.fan_pwm_get(&card) >= 0)
            addTachometer(nouveau_fan_pwm, title, GPU_FAN_PWM_CYCLE, card.card_index);
    }
    
    if (card.volt.get && card.volt.get(&card) >= 0/*card.voltage_get && card.voltage.supported*/) {
        nv_debug(device, "registering voltage sensors...\n");
        snprintf(key, 5, KEY_FORMAT_GPU_VOLTAGE, card.card_index);
        addSensorForKey(key, TYPE_FP2E, TYPE_FPXX_SIZE, kFakeSMCVoltageSensor, 0);
    }
    
    registerService();
    
    nv_info(device, "started\n");
    
    return true;
}
Пример #12
0
int
nv40_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x40:
		device->cname = "NV40";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x41:
		device->cname = "NV41";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x42:
		device->cname = "NV42";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x43:
		device->cname = "NV43";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv41_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x45:
		device->cname = "NV45";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv40_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x47:
		device->cname = "G70";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv47_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x49:
		device->cname = "G71";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4b:
		device->cname = "G73";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv40_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv49_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv41_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x44:
		device->cname = "NV44";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x46:
		device->cname = "G72";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4a:
		device->cname = "NV44A";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv44_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv44_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4c:
		device->cname = "C61";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x4e:
		device->cname = "C51";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv4e_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv4e_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x63:
		device->cname = "C73";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x67:
		device->cname = "C67";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	case 0x68:
		device->cname = "C68";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv40_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv40_therm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv4c_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv31_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv46_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv40_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv44_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
		break;
	default:
		nv_fatal(device, "unknown Curie chipset\n");
		return -EINVAL;
	}

	return 0;
}
bool GeforceSensors::start(IOService *provider)
{
	HWSensorsDebugLog("Starting...");
	
	if (!super::start(provider))
        return false;
        
    struct nouveau_device *device = &card;
    
    // map device memory
    if ((device->pcidev = (IOPCIDevice*)provider)) {
        
        device->pcidev->setMemoryEnable(true);
        
        if ((device->mmio = device->pcidev->mapDeviceMemoryWithIndex(0))) {
            nv_debug(device, "memory mapped successfully\n");
        }
        else {
            HWSensorsFatalLog("failed to map memory");
            return false;
        }
    }
    else {
        HWSensorsFatalLog("failed to assign PCI device");
        return false;
    }
    
    card.card_index = -1;

    if (OSData *multiboard_capable = OSDynamicCast(OSData, provider->getProperty("rm_multiboard_capable"))) {
        if (0x1 == *((UInt32*)multiboard_capable->getBytesNoCopy())) {
            if (OSData *board_number = OSDynamicCast(OSData, provider->getProperty("rm_board_number"))) {
                UInt8 index = *((UInt32*)board_number->getBytesNoCopy());
                card.card_index = takeGPUIndex(index);
            }
        }
    }
    
    if (card.card_index < 0)
        card.card_index = takeVacantGPUIndex();
    
    if (card.card_index < 0) {
        HWSensorsFatalLog("failed to take vacant GPU index");
        return false;
    }
    
    // identify chipset
    if (!nouveau_identify(device)) {
        releaseGPUIndex(card.card_index);
        return false;
    }
    
    // shadow and parse bios
    
    //try to load bios from registry first from "vbios" property created by Chameleon boolloader
    if (OSData *vbios = OSDynamicCast(OSData, provider->getProperty("vbios"))) {
        device->bios.size = vbios->getLength();
        device->bios.data = (u8*)IOMalloc(card.bios.size);
        memcpy(device->bios.data, vbios->getBytesNoCopy(), device->bios.size);
    }
    
    if (!device->bios.data || !device->bios.size || nouveau_bios_score(device, true) < 1)
        if (!nouveau_bios_shadow(device)) {
            if (device->bios.data && device->bios.size) {
                IOFree(card.bios.data, card.bios.size);
                device->bios.data = NULL;
                device->bios.size = 0;
            }
            
            nv_fatal(device, "unable to shadow VBIOS\n");
            
            releaseGPUIndex(card.card_index);
            card.card_index = -1;
            return false;
        }
    
    nouveau_vbios_init(device);
    nouveau_bios_parse(device);
    
    // initialize funcs and variables
    if (!nouveau_init(device)) {
        nv_error(device, "unable to initialize monitoring driver\n");
        releaseGPUIndex(card.card_index);
        card.card_index = -1;
        return false;
    }
    
    nv_info(device, "chipset: %s (NV%02X) bios: %02x.%02x.%02x.%02x\n", device->cname, device->chipset, device->bios.version.major, device->bios.version.chip, device->bios.version.minor, device->bios.version.micro);
    
    if (device->card_type < NV_C0) {
        // init i2c structures
        nouveau_i2c_create(device);
        
        // setup nouveau i2c sensors
        nouveau_i2c_probe(device);
    }
    
    // Register sensors
    char key[5];
    if (card.core_temp_get || card.board_temp_get) {
        nv_debug(device, "registering i2c temperature sensors...\n");
        
        if (card.core_temp_get && card.board_temp_get) {
            snprintf(key, 5, KEY_FORMAT_GPU_DIODE_TEMPERATURE, card.card_index);
            addSensor(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_core);
            
            snprintf(key, 5, KEY_FORMAT_GPU_HEATSINK_TEMPERATURE, card.card_index);
            addSensor(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_board);
        }
        else if (card.core_temp_get) {
            snprintf(key, 5, KEY_FORMAT_GPU_DIODE_TEMPERATURE, card.card_index);
            addSensor(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_core);
        }
        else if (card.board_temp_get) {
            snprintf(key, 5, KEY_FORMAT_GPU_HEATSINK_TEMPERATURE, card.card_index);
            addSensor(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_board);
        }
    }
    else if (card.temp_get)
    {
        nv_debug(device, "registering temperature sensors...\n");
        
        snprintf(key, 5, KEY_FORMAT_GPU_DIODE_TEMPERATURE, card.card_index);
        addSensor(key, TYPE_SP78, 2, kFakeSMCTemperatureSensor, nouveau_temp_diode);
    }
    
    int arg_value = 1;

    if (card.clocks_get && !PE_parse_boot_argn("-gpusensors-no-clocks", &arg_value, sizeof(arg_value))) {
        nv_debug(device, "registering clocks sensors...\n");
        
        if (card.clocks_get(&card, nouveau_clock_core) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_FREQUENCY, card.card_index);
            addSensor(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_core);
        }
        
//        if (card.clocks_get(&card, nouveau_clock_shader) > 0) {
//            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_SHADER_FREQUENCY, card.card_index);
//            addSensor(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_shader);
//        }
        
        if (card.clocks_get(&card, nouveau_clock_rop) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_ROP_FREQUENCY, card.card_index);
            addSensor(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_rop);
        }
        
        if (card.clocks_get(&card, nouveau_clock_memory) > 0) {
            snprintf(key, 5, KEY_FAKESMC_FORMAT_GPU_MEMORY_FREQUENCY, card.card_index);
            addSensor(key, TYPE_UI32, TYPE_UI32_SIZE, kFakeSMCFrequencySensor, nouveau_clock_memory);
        }
    }
    
    if (card.fan_pwm_get || card.fan_rpm_get) {
        nv_debug(device, "registering PWM sensors...\n");

        char title[DIAG_FUNCTION_STR_LEN];
        snprintf (title, DIAG_FUNCTION_STR_LEN, "GPU %X", card.card_index + 1);
        
        if (card.fan_rpm_get && card.fan_rpm_get(device) >= 0)
            addTachometer(nouveau_fan_rpm, title, GPU_FAN_RPM, card.card_index);
        
        if (card.fan_pwm_get && card.fan_pwm_get(device) >= 0)
            addTachometer(nouveau_fan_pwm, title, GPU_FAN_PWM_CYCLE, card.card_index);
    }
    
    if (card.voltage_get && card.voltage.supported) {
        nv_debug(device, "registering voltage sensors...\n");
        snprintf(key, 5, KEY_FORMAT_GPU_VOLTAGE, card.card_index);
        addSensor(key, TYPE_FP2E, TYPE_FPXX_SIZE, kFakeSMCVoltageSensor, 0);
    }
    
    registerService();
    
    nv_info(device, "started\n");
    
    return true;
}
Пример #14
0
int
nve0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0xe4:
		device->cname = "GK104";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xe7:
		device->cname = "GK107";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xe6:
		device->cname = "GK106";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  gk104_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xea:
		device->cname = "GK20A";
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &gk20a_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gk20a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk20a_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &gk20a_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_graph_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
		break;
	case 0xf0:
		device->cname = "GK110";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
		break;
	case 0xf1:
		device->cname = "GK110B";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
		break;
	case 0x108:
		device->cname = "GK208";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nve0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gf100_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Kepler chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #15
0
int
nv50_identify(struct nvkm_device *device)
{
	switch (device->chipset) {
	case 0x50:
		device->cname = "G80";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  nv50_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
		break;
	case 0x84:
		device->cname = "G84";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x86:
		device->cname = "G86";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x92:
		device->cname = "G92";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x94:
		device->cname = "G94";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x96:
		device->cname = "G96";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0x98:
		device->cname = "G98";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa0:
		device->cname = "G200";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  g84_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  g84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xaa:
		device->cname = "MCP77/MCP78";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  mcp77_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp77_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xac:
		device->cname = "MCP79/MCP7A";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] =  mcp77_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &g84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  g98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp77_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
		break;
	case 0xa3:
		device->cname = "GT215";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa5:
		device->cname = "GT216";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xa8:
		device->cname = "GT218";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gt215_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  gt215_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	case 0xaf:
		device->cname = "MCP89";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] =  g94_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] =  g94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_FUSE   ] =  &nv50_fuse_oclass;
		device->oclass[NVDEV_SUBDEV_CLK    ] = &gt215_clk_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  mcp89_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  g98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  g94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  mcp89_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv50_mmu_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PMU    ] =  gt215_pmu_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
		break;
	default:
		nv_fatal(device, "unknown Tesla chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #16
0
int
nv50_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x50:
		device->cname = "G80";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv50_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv50_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv50_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv50_perfmon_oclass;
		break;
	case 0x84:
		device->cname = "G84";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0x86:
		device->cname = "G86";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0x92:
		device->cname = "G92";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv50_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv50_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv84_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0x94:
		device->cname = "G94";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0x96:
		device->cname = "G96";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv94_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0x98:
		device->cname = "G98";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0xa0:
		device->cname = "G200";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv50_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nv84_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv84_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nv84_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva0_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0xaa:
		device->cname = "MCP77/MCP78";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0xac:
		device->cname = "MCP79/MCP7A";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] =  nvaa_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nv84_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv98_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaa_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
		break;
	case 0xa3:
		device->cname = "GT215";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
		break;
	case 0xa5:
		device->cname = "GT216";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
		break;
	case 0xa8:
		device->cname = "GT218";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nva3_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nva3_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
		break;
	case 0xaf:
		device->cname = "MCP89";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvaf_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nv98_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv94_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nvaf_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nva3_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] =  nva3_perfmon_oclass;
		break;
	default:
		nv_fatal(device, "unknown Tesla chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #17
0
int
nv10_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x10:
		device->cname = "NV10";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x15:
		device->cname = "NV15";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x16:
		device->cname = "NV16";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x1a:
		device->cname = "nForce";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv1a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x11:
		device->cname = "NV11";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv10_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x17:
		device->cname = "NV17";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x1f:
		device->cname = "nForce2";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv1a_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x18:
		device->cname = "NV18";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv04_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nv04_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv10_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv10_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Celsius chipset\n");
		return -EINVAL;
	}

	return 0;
}
Пример #18
0
int
nvc0_identify(struct nouveau_device *device)
{
    switch (device->chipset) {
    case 0xc0:
        device->cname = "GF100";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xc4:
        device->cname = "GF104";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xc3:
        device->cname = "GF106";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xce:
        device->cname = "GF114";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xcf:
        device->cname = "GF116";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xc1:
        device->cname = "GF108";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xc8:
        device->cname = "GF110";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
        break;
    case 0xd9:
        device->cname = "GF119";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
        break;
    case 0xd7:
        device->cname = "GF117";
        device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
        device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
        device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
        device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
        device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
        device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
        device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
        device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
        device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
        device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
        device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
        device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
        device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
        device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
        device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
        device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
        device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
        device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
        device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
        device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;
        device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
        device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
        device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
        device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
        device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
        break;
    default:
        nv_fatal(device, "unknown Fermi chipset\n");
        return -EINVAL;
    }

    return 0;
}
Пример #19
0
bool nv40_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
        case 0x40:
            device->cname = "NV40";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
           
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x41:
            device->cname = "NV41";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x42:
            device->cname = "NV42";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x43:
            device->cname = "NV43";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x45:
            device->cname = "NV45";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x47:
            device->cname = "G70";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x49:
            device->cname = "G71";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x4b:
            device->cname = "G73";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x44:
            device->cname = "NV44";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x46:
            device->cname = "G72";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x4a:
            device->cname = "NV44A";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x4c:
            device->cname = "C61";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x4e:
            device->cname = "C51";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x63:
            device->cname = "C73";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x67:
            device->cname = "C67";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        case 0x68:
            device->cname = "C68";
            device->gpio_init = nv10_gpio_init;
            device->gpio_sense = nv10_gpio_sense;
            
//            device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
//            device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
//            device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
//            device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
//            device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
//            device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
//            device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
//            device->oclass[NVDEV_SUBDEV_FB     ] = &nv40_fb_oclass;
//            device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
//            device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
//            device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
//            device->oclass[NVDEV_ENGINE_FIFO   ] = &nv40_fifo_oclass;
//            device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
//            device->oclass[NVDEV_ENGINE_GR     ] = &nv40_graph_oclass;
//            device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
//            device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
            break;
        default:
            nv_fatal(device, "unknown Curie chipset\n");
            return false;
	}
    
	return true;
}