static int
nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
{
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numInputs; ++i) {
offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
for (c = 0; c < 4; ++c)
info->in[i].slot[c] = (offset + c * 0x4) / 4;
}
return 0;
}
static int
nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
{
unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numInputs; ++i) {
offset = nvc0_shader_input_address(info->in[i].sn,
info->in[i].si, ubase);
if (info->in[i].patch && offset >= 0x20)
offset = 0x20 + info->in[i].si * 0x10;
if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
info->in[i].mask &= 3;
for (c = 0; c < 4; ++c)
info->in[i].slot[c] = (offset + c * 0x4) / 4;
}
return 0;
}
static int
nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
{
unsigned i, c, n;
for (n = 0, i = 0; i < info->numInputs; ++i) {
switch (info->in[i].sn) {
case TGSI_SEMANTIC_INSTANCEID: /* for SM4 only, in TGSI they're SVs */
case TGSI_SEMANTIC_VERTEXID:
info->in[i].mask = 0x1;
info->in[i].slot[0] =
nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
continue;
default:
break;
}
for (c = 0; c < 4; ++c)
info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
++n;
}
return 0;
}
