/* detect hardware features */
static int nvt_hw_detect(struct nvt_dev *nvt)
{
unsigned long flags;
u8 chip_major, chip_minor;
int ret = 0;
nvt_efm_enable(nvt);
/* Check if we're wired for the alternate EFER setup */
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
if (chip_major == 0xff) {
nvt->cr_efir = CR_EFIR2;
nvt->cr_efdr = CR_EFDR2;
nvt_efm_enable(nvt);
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
}
chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
if (chip_major != CHIP_ID_HIGH &&
(chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
ret = -ENODEV;
nvt_efm_disable(nvt);
spin_lock_irqsave(&nvt->nvt_lock, flags);
nvt->chip_major = chip_major;
nvt->chip_minor = chip_minor;
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
return ret;
}
/* detect hardware features */
static void nvt_hw_detect(struct nvt_dev *nvt)
{
const char *chip_name;
int chip_id;
nvt_efm_enable(nvt);
/* Check if we're wired for the alternate EFER setup */
nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
if (nvt->chip_major == 0xff) {
nvt->cr_efir = CR_EFIR2;
nvt->cr_efdr = CR_EFDR2;
nvt_efm_enable(nvt);
nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
}
nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
chip_id = nvt->chip_major << 8 | nvt->chip_minor;
chip_name = nvt_find_chip(nvt, chip_id);
/* warn, but still let the driver load, if we don't know this chip */
if (!chip_name)
dev_warn(&nvt->pdev->dev,
"unknown chip, id: 0x%02x 0x%02x, it may not work...",
nvt->chip_major, nvt->chip_minor);
else
dev_info(&nvt->pdev->dev,
"found %s or compatible: chip id: 0x%02x 0x%02x",
chip_name, nvt->chip_major, nvt->chip_minor);
nvt_efm_disable(nvt);
}
/* dump current cir register contents */
static void cir_dump_regs(struct nvt_dev *nvt)
{
nvt_efm_enable(nvt);
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
pr_reg(" * CR CIR ACTIVE : 0x%x\n",
nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
nvt_efm_disable(nvt);
pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
}
/* dump current cir wake register contents */
static void cir_wake_dump_regs(struct nvt_dev *nvt)
{
u8 i, fifo_len;
nvt_efm_enable(nvt);
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
pr_reg("%s: Dump CIR WAKE logical device registers:\n",
NVT_DRIVER_NAME);
pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
nvt_efm_disable(nvt);
pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
pr_reg(" * IRCON: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
pr_reg(" * IRSTS: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
pr_reg(" * IREN: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
pr_reg(" * FIFO CMP DEEP: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
pr_reg(" * FIFO CMP TOL: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
pr_reg(" * FIFO COUNT: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
pr_reg(" * SLCH: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
pr_reg(" * SLCL: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
pr_reg(" * FIFOCON: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
pr_reg(" * SRXFSTS: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
pr_reg(" * WR FIFO DATA: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
pr_reg(" * RD FIFO ONLY: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
pr_reg(" * FIFO IGNORE: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
pr_reg(" * IRFSM: 0x%x\n",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
pr_reg("* Contents = ");
for (i = 0; i < fifo_len; i++)
printk(KERN_CONT "%02x ",
nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
printk(KERN_CONT "\n");
}
/* detect hardware features */
static int nvt_hw_detect(struct nvt_dev *nvt)
{
unsigned long flags;
u8 chip_major, chip_minor;
int ret = 0;
char chip_id[12];
bool chip_unknown = false;
nvt_efm_enable(nvt);
/* Check if we're wired for the alternate EFER setup */
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
if (chip_major == 0xff) {
nvt->cr_efir = CR_EFIR2;
nvt->cr_efdr = CR_EFDR2;
nvt_efm_enable(nvt);
chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
}
chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
/* these are the known working chip revisions... */
switch (chip_major) {
case CHIP_ID_HIGH_667:
strcpy(chip_id, "w83667hg\0");
if (chip_minor != CHIP_ID_LOW_667)
chip_unknown = true;
break;
case CHIP_ID_HIGH_677B:
strcpy(chip_id, "w83677hg\0");
if (chip_minor != CHIP_ID_LOW_677B2 &&
chip_minor != CHIP_ID_LOW_677B3)
chip_unknown = true;
break;
case CHIP_ID_HIGH_677C:
strcpy(chip_id, "w83677hg-c\0");
if (chip_minor != CHIP_ID_LOW_677C)
chip_unknown = true;
break;
default:
strcpy(chip_id, "w836x7hg\0");
chip_unknown = true;
break;
}
/* warn, but still let the driver load, if we don't know this chip */
if (chip_unknown)
nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
"it may not work...", chip_id, chip_major, chip_minor);
else
nvt_dbg("%s: chip id: 0x%02x 0x%02x",
chip_id, chip_major, chip_minor);
nvt_efm_disable(nvt);
spin_lock_irqsave(&nvt->nvt_lock, flags);
nvt->chip_major = chip_major;
nvt->chip_minor = chip_minor;
spin_unlock_irqrestore(&nvt->nvt_lock, flags);
return ret;
}