void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, uint64_t max_addr, uint64_t align, char *name) { uint64_t addr; addr = octeon_phy_mem_named_block_alloc(cvmx_bootmem_desc, size, min_addr, max_addr, align, name); if (addr) return cvmx_phys_to_ptr(addr); else return NULL; }
void octeon_hal_init(void) { /* Make sure we got the boot descriptor block */ if ((octeon_boot_desc_ptr == (void *)0xEADBEEFULL)) panic("Boot descriptor block wasn't passed properly\n"); octeon_bootinfo = octeon_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); spin_lock_init(&octeon_led_lock); #ifndef CONFIG_CAVIUM_OCTEON_SIMULATOR /* Only enable the LED controller if we're running on a CN38XX or CN58XX. The CN30XX and CN31XX don't have an LED controller */ if ((current_cpu_data.cputype == CPU_CAVIUM_CN38XX) || (current_cpu_data.cputype == CPU_CAVIUM_CN58XX)) { octeon_write_csr(OCTEON_LED_EN, 0); octeon_write_csr(OCTEON_LED_PRT, 0); octeon_write_csr(OCTEON_LED_DBG, 0); octeon_write_csr(OCTEON_LED_PRT_FMT, 0); octeon_write_csr(OCTEON_LED_UDD_CNTX(0), 32); octeon_write_csr(OCTEON_LED_UDD_CNTX(1), 32); octeon_write_csr(OCTEON_LED_UDD_DATX(0), 0); octeon_write_csr(OCTEON_LED_UDD_DATX(1), 0); octeon_write_csr(OCTEON_LED_EN, 1); } #endif #if CONFIG_CAVIUM_RESERVE32 { cvmx_bootmem_desc_t *bootmem_desc = octeon_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); octeon_reserve32_memory = octeon_phy_mem_named_block_alloc(bootmem_desc, CONFIG_CAVIUM_RESERVE32<<20, 0, 0, 2<<20, "CAVIUM_RESERVE32"); if (octeon_reserve32_memory == 0) printk("Failed to allocate CAVIUM_RESERVE32 memory area\n"); } #endif #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 if (octeon_read_csr(OCTEON_L2D_FUS3) & (3ull<<34)) { printk("Skipping L2 locking due to reduced L2 cache size\n"); } else { extern asmlinkage void octeon_handle_irq(void); uint64_t ebase = read_c0_ebase() & 0x3ffff000; #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB octeon_l2_lock_range(ebase, 0x100); /* TLB refill */ #endif #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION octeon_l2_lock_range(ebase + 0x180, 0x80); /* General exception */ #endif #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT octeon_l2_lock_range(ebase + 0x200, 0x80); /* Interrupt handler */ #endif #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT octeon_l2_lock_range((uint64_t)octeon_handle_irq, 0x280); #endif #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY octeon_l2_lock_range((uint64_t)memcpy, 0x480); #endif } #endif }