static void cosmo_hdmi_pad_init(void)
{
u32 r;
/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
omap_mux_init_signal("hdmi_hpd.hdmi_hpd",
OMAP_PIN_INPUT_PULLDOWN);
/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
omap_mux_init_signal("hdmi_ddc_scl.hdmi_ddc_scl",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hdmi_ddc_sda.hdmi_ddc_sda",
OMAP_PIN_INPUT_PULLUP);
/* strong pullup on DDC lines using unpublished register */
r = ((1 << 24) | (1 << 28)) ;
omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1);
gpio_request(GPIO_HDMI_HPD, NULL);
omap_mux_init_gpio(GPIO_HDMI_HPD, OMAP_PIN_INPUT | OMAP_PULL_ENA);
gpio_direction_input(GPIO_HDMI_HPD);
}
static void tuna_hdmi_mux_init(void)
{
u32 r;
/* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
omap_mux_init_signal("hdmi_hpd.hdmi_hpd",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("gpmc_wait2.gpio_100",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hdmi_cec.hdmi_cec",
OMAP_PIN_INPUT_PULLUP);
/* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
omap_mux_init_signal("hdmi_ddc_scl.hdmi_ddc_scl",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hdmi_ddc_sda.hdmi_ddc_sda",
OMAP_PIN_INPUT_PULLUP);
/* strong pullup on DDC lines using unpublished register */
r = ((1 << 24) | (1 << 28)) ;
omap4_ctrl_pad_writel(r, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1);
}
void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
if (omap_hsmmc_done)
return;
omap_hsmmc_done = 1;
if (!(cpu_is_omap44xx() || cpu_is_omap54xx())) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else if (cpu_is_omap44xx()) {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
} else if (cpu_is_omap54xx()) {
control_pbias_offset =
OMAP5_CTRL_MODULE_CORE_PAD_CONTROL_PBIAS;
}
for (; controllers->mmc; controllers++)
omap_hsmmc_init_one(controllers, controllers->mmc);
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
if (machine_is_omap3_pandora()) {
/* needed for gpio_126 - gpio_129 to work correctly */
reg = omap_ctrl_readl(control_pbias_offset);
reg &= ~OMAP343X_PBIASLITEVMODE1;
omap_ctrl_writel(reg, control_pbias_offset);
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (; controllers->mmc; controllers++)
omap_init_hsmmc(controllers, controllers->mmc);
}
static inline void __init board_serial_init(void)
{
omap_serial_init_port_pads(0, tablet_uart1_pads,
ARRAY_SIZE(tablet_uart1_pads), &tablet_uart_info_nocts);
omap_serial_init_port_pads(1, tablet_uart2_pads,
ARRAY_SIZE(tablet_uart2_pads), &tablet_uart_info);
/* UART3 only for debug console on OTG DP/DM pins */
if (uart3_on_usb) {
omap_serial_init_port_pads(2, tablet_uart3_pads,
ARRAY_SIZE(tablet_uart3_pads), &tablet_uart_info_nocts);
/* set usb-otg phy to gpio mode */
omap4_ctrl_pad_writel((1UL << 29),
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE);
} else
omap_serial_init_port_pads(2, no_uart_pads,
0, &tablet_uart_info_uncon);
/* We don't use uart4. */
/* omap_serial_init_port_pads(3, tablet_uart4_pads,
* ARRAY_SIZE(tablet_uart4_pads), &tablet_uart_info_uncon);
*/
}
static void cosmo_dsi_phy_init(void)
{
u32 reg;
/* Enable 3 lanes (0 ~ 2) in DSI2 */
/* Disable pull down */
reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
reg &= ~OMAP4_DSI2_LANEENABLE_MASK;
reg |= 0x1F << OMAP4_DSI2_LANEENABLE_SHIFT;
reg &= ~OMAP4_DSI2_PIPD_MASK;
reg |= 0x1F << OMAP4_DSI2_PIPD_SHIFT;
omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
#ifdef CONFIG_MACH_LGE_COSMO //mo2sanghyun.lee
gpio_request(HDMI_GPIO_60 , "hdmi_gpio_60");
gpio_request(HDMI_GPIO_41 , "hdmi_gpio_41");
gpio_direction_output(HDMI_GPIO_60, 1);
gpio_direction_output(HDMI_GPIO_41, 0);
#endif
#if defined(CONFIG_DSI_CMD_MODE)
omap_mux_init_signal("gpmc_ncs6.dsi2_te0", OMAP_PIN_INPUT);
#endif
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
if ((machine_is_omap_hummingbird() &&
(system_rev > HUMMINGBIRD_EVT0B)) ||
machine_is_omap_ovation())
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
else
reg |= (OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (; controllers->mmc; controllers++)
omap_init_hsmmc(controllers, controllers->mmc);
}
void __init omap4_tuna_display_init(void)
{
struct panel_s6e8aa0_data *panel;
if (omap4_tuna_get_revision() ==
(omap4_tuna_get_type() == TUNA_TYPE_MAGURO ? 2 : 1)) {
/*
* Older devices were not calibrated the same way as newer
* devices. These values are probably not correct, but the older
* devices tested look closer to the newer devices with these
* values than they do using the same register values as the
* newer devices.
*/
tuna_oled_data_m3.factory_info = &tuna_oled_factory_info_m2t1;
} else if (omap4_tuna_get_revision() <= 1) {
tuna_oled_data_m3.factory_info = &tuna_oled_factory_info_old;
}
if (panel_id == SM2)
panel = &tuna_oled_data_sm2;
else
panel = &tuna_oled_data_m3;
tuna_oled_device.data = panel;
omap4_ctrl_pad_writel(0x1FF80000,
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
omap_mux_init_gpio(panel->reset_gpio, OMAP_PIN_OUTPUT);
pr_info("Using %ps\n", panel->factory_info);
omap_vram_set_sdram_vram(TUNA_FB_RAM_SIZE, 0);
omapfb_set_platform_data(&tuna_fb_pdata);
tuna_hdmi_mux_init();
omap_display_init(&tuna_dss_data);
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
int i;
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc) {
pr_debug("MMC%d: no such controller\n", c->mmc);
continue;
}
if (mmc) {
pr_debug("MMC%d: already configured\n", c->mmc);
continue;
}
mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
GFP_KERNEL);
if (!mmc) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
}
if (cpu_is_ti816x())
mmc->version = MMC_CTRL_VERSION_2;
if (c->name)
strncpy(hc->name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc->name, ARRAY_SIZE(hc->name),
"mmc%islot%i", c->mmc, 1);
mmc->slots[0].name = hc->name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
MMC_VDD_26_27 |
MMC_VDD_27_28 |
MMC_VDD_29_30 |
MMC_VDD_30_31 |
MMC_VDD_31_32;
else
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_ti81xx())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
cpu_is_ti814x())
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* Omap3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
/* FALLTHROUGH */
case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(mmc);
continue;
}
hsmmc_data[c->mmc - 1] = mmc;
}
if (!cpu_is_ti81xx())
omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
else
omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC);
/* pass the device nodes back to board setup code */
for (c = controllers; c->mmc; c++) {
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc)
continue;
c->dev = mmc->dev;
}
done:
for (i = 0; i < nr_hsmmc; i++)
kfree(hsmmc_data[i]);
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
int i;
u32 reg;
int controller_cnt = 0;
printk(">>> omap2_hsmmc_init\n");
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
}
else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
}
else {
control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
struct hsmmc_controller *hc = hsmmc + controller_cnt;
struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt];
if (!c->mmc || c->mmc > nr_hsmmc) {
printk("MMC%d: no such controller\n", c->mmc);
continue;
}
if (mmc) {
printk("MMC%d: already configured\n", c->mmc);
continue;
}
mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
if (!mmc) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
}
if (c->name)
strncpy(hc->name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc->name, ARRAY_SIZE(hc->name),
"mmc%islot%i", c->mmc, 1);
#ifdef CONFIG_TIWLAN_SDIO
if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) {
mmc->slots[0].embedded_sdio = &omap_wifi_emb_data;
mmc->slots[0].register_status_notify = &omap_wifi_status_register;
mmc->slots[0].card_detect = &omap_wifi_status;
}
#endif
mmc->slots[0].name = hc->name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
/* Register offset Mapping */
if (cpu_is_omap44xx())
mmc->regs_map = (u16 *) omap4_mmc_reg_map;
else
mmc->regs_map = (u16 *) omap3_mmc_reg_map;
if (!cpu_is_omap44xx())
mmc->get_context_loss_count = hsmmc_get_context_loss;
//&*&*&*SJ1_20110607, Add SIM card detection.
#if defined (CONFIG_SIM_CARD_DETECTION) && defined (CONFIG_CHANGE_INAND_MMC_SCAN_INDEX)
mmc->slots[0].sim_switch_pin = c->gpio_sim_cd;
#endif
//&*&*&*SJ2_20110607, Add SIM card detection.
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].cd_active_high = c->cd_active_high;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx()) {
if (omap_rev() > OMAP4430_REV_ES1_0)
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
mmc->slots[0].features |= HSMMC_DVFS_24MHZ_CONST;
if (c->mmc >= 3 && c->mmc <= 5) {
mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK;
mmc->get_context_loss_count =
hsmmc_get_context_loss;
}
}
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
}
else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* Omap3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
/* FALLTHROUGH */
case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195;
#endif
break;
case 4:
case 5:
/* TODO Update required */
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195;
#endif
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(mmc);
continue;
}
hsmmc_data[controller_cnt] = mmc;
omap2_init_mmc(hsmmc_data[controller_cnt], c->mmc);
controller_cnt++;
}
/* pass the device nodes back to board setup code */
controller_cnt = 0;
for (c = controllers; c->mmc; c++) {
struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt];
if (!c->mmc || c->mmc > nr_hsmmc)
continue;
c->dev = mmc->dev;
controller_cnt++;
}
done:
for (i = 0; i < controller_cnt; i++)
kfree(hsmmc_data[i]);
printk("<<< omap2_hsmmc_init\n");
}
int omap_uart_cts_wakeup(int uart_no, int state)
{
struct uart_omap_port *up = ui[uart_no];
struct omap_uart_port_info *omap_up_info = up->pdev->dev.platform_data;
u16 offset = 0; /* 32-bit align */
u32 v;
/* No CTS based Wake-ups are enabled. If enabled this would
* hold the CTS Pad Conf Register offset.
*/
if (!omap_up_info->cts_padconf) {
dev_dbg(up->port.dev, "No CTS wake-up for UART %d\n", uart_no);
return -EPERM;
}
if (state) {
/*
* Enable the CTS for io pad wakeup
*/
dev_dbg(up->port.dev, "Enable CTS wakeup for UART %d", uart_no);
offset = omap_up_info->cts_padconf & ~0x3; /* 32-bit align */
if (cpu_is_omap44xx())
v = omap4_ctrl_pad_readl(offset);
else
v = omap_ctrl_readl(offset);
if (omap_up_info->cts_padconf & 0x2) {
omap_up_info->cts_padvalue = 0xFFFF0000 & v;
v |= (((OMAP_WAKEUP_EN | OMAP_OFF_PULL_EN |
OMAP_OFF_PULL_UP | OMAP_OFFOUT_EN |
OMAP_OFF_EN | OMAP_PULL_UP)) << 16);
} else {
omap_up_info->cts_padvalue = 0x0000FFFF & v;
v |= ((OMAP_WAKEUP_EN | OMAP_OFF_PULL_EN |
OMAP_OFF_PULL_UP | OMAP_OFFOUT_EN |
OMAP_OFF_EN | OMAP_PULL_UP));
}
if (cpu_is_omap44xx())
omap4_ctrl_pad_writel(v, offset);
else
omap_ctrl_writel(v, offset);
/*
* Enable the CTS for module level wakeup
*/
serial_out(up, UART_OMAP_WER,
serial_in(up, UART_OMAP_WER) | 0x1);
} else {
dev_dbg(up->port.dev, "Disable CTS wakeup for UART%d\n",
uart_no);
/*
* Disable the CTS capability for io pad wakeup
*/
offset = omap_up_info->cts_padconf & ~0x3; /* 32-bit align */
if (cpu_is_omap44xx())
v = omap4_ctrl_pad_readl(offset);
else
v = omap_ctrl_readl(offset);
v = ((omap_up_info->cts_padconf & 0x2 ? 0x0000FFFF : 0xFFFF0000)
& v) | omap_up_info->cts_padvalue;
if (cpu_is_omap44xx())
omap4_ctrl_pad_writel(v, offset);
else
omap_ctrl_writel(v, offset);
}
return 0;
}
static struct omap_hwmod_mux_info * __init
setup_4430_usbhs_io_mux(struct platform_device *pdev,
const enum usbhs_omap_port_mode *port_mode)
{
const struct omap_device_pad *pads[OMAP3_HS_USB_PORTS];
int pads_cnt[OMAP3_HS_USB_PORTS];
switch (port_mode[0]) {
case OMAP_EHCI_PORT_MODE_PHY:
pads[0] = port1_phy_pads;
pads_cnt[0] = ARRAY_SIZE(port1_phy_pads);
break;
case OMAP_EHCI_PORT_MODE_TLL:
pads[0] = port1_tll_pads;
pads_cnt[0] = ARRAY_SIZE(port1_tll_pads);
/* Errata i687: set I/O drive strength to 1 */
if (cpu_is_omap443x()) {
u32 val;
val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2);
val |= OMAP4_USBB1_DR0_DS_MASK;
omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2);
}
break;
case OMAP_EHCI_PORT_MODE_HSIC:
pads[0] = port1_hsic_pads;
pads_cnt[0] = ARRAY_SIZE(port1_hsic_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
pads[0] = port1_6pin_pads;
pads_cnt[0] = ARRAY_SIZE(port1_6pin_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
pads[0] = port1_4pin_pads;
pads_cnt[0] = ARRAY_SIZE(port1_4pin_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
pads[0] = port1_3pin_pads;
pads_cnt[0] = ARRAY_SIZE(port1_3pin_pads);
break;
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
pads[0] = port1_2pin_pads;
pads_cnt[0] = ARRAY_SIZE(port1_2pin_pads);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
pads_cnt[0] = 0;
break;
}
switch (port_mode[1]) {
case OMAP_EHCI_PORT_MODE_PHY:
pads[1] = port2_phy_pads;
pads_cnt[1] = ARRAY_SIZE(port2_phy_pads);
break;
case OMAP_EHCI_PORT_MODE_TLL:
pads[1] = port2_tll_pads;
pads_cnt[1] = ARRAY_SIZE(port2_tll_pads);
/* Errata i687: set I/O drive strength to 1 */
if (cpu_is_omap443x()) {
u32 val;
val = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2);
val |= OMAP4_USBB2_DR0_DS_MASK;
omap4_ctrl_pad_writel(val, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_2);
}
break;
case OMAP_EHCI_PORT_MODE_HSIC:
pads[1] = port2_hsic_pads;
pads_cnt[1] = ARRAY_SIZE(port2_hsic_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
pads[1] = port2_6pin_pads;
pads_cnt[1] = ARRAY_SIZE(port2_6pin_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
pads[1] = port2_4pin_pads;
pads_cnt[1] = ARRAY_SIZE(port2_4pin_pads);
break;
case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
pads[1] = port2_3pin_pads;
pads_cnt[1] = ARRAY_SIZE(port2_3pin_pads);
break;
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
pads[1] = port2_2pin_pads;
pads_cnt[1] = ARRAY_SIZE(port2_3pin_pads);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
pads_cnt[1] = 0;
break;
}
switch (port_mode[2]) {
case OMAP_EHCI_PORT_MODE_HSIC:
pads[2] = port3_hsic_pads;
pads_cnt[2] = ARRAY_SIZE(port3_hsic_pads);
break;
case OMAP_USBHS_PORT_MODE_UNUSED:
default:
pads_cnt[2] = 0;
break;
}
return omap_hwmod_mux_array_init(pdev, pads, pads_cnt, port_mode);
}