struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
struct omap_uart_s *s = (struct omap_uart_s *)
qemu_mallocz(sizeof(struct omap_uart_s));
s->base = base;
s->fclk = fclk;
s->irq = irq;
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
0);
#endif
return s;
}
struct omap_uart_s *omap_uart_init(hwaddr base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
struct omap_uart_s *s = g_new0(struct omap_uart_s, 1);
s->base = base;
s->fclk = fclk;
s->irq = irq;
s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_new(label, "null"),
DEVICE_NATIVE_ENDIAN);
return s;
}
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
{
target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
omap_uart_writefn, s);
s->ta = ta;
cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
return s;
}
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
{
/* TODO: Should reuse or destroy current s->serial */
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
0);
#endif
}
/*if the clock source of gptimer changes, rate must be regenerated*/
void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer)
{
timer->rate = omap_clk_getrate(timer->clk);
}