static int lirc_rx51_free_port(struct lirc_rx51 *lirc_rx51)
{
omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
free_irq(lirc_rx51->irq_num, lirc_rx51);
lirc_rx51_off(lirc_rx51);
omap_dm_timer_disable(lirc_rx51->pwm_timer);
omap_dm_timer_disable(lirc_rx51->pulse_timer);
omap_dm_timer_free(lirc_rx51->pwm_timer);
omap_dm_timer_free(lirc_rx51->pulse_timer);
lirc_rx51->wbuf_index = -1;
return 0;
}
static void set_gptimer_pwm_vibrator(int on)
{
unsigned long flags;
if (pwm_timer == NULL) {
pr_err(KERN_ERR "vibrator pwm timer is NULL\n");
return;
}
spin_lock_irqsave(&vibe__timer_lock, flags);
if (on) {
if(!vibe_timer_state) {
gpio_set_value(GPIO_VIB_EN, 1);
omap_dm_timer_enable(pwm_timer);
omap_dm_timer_set_match(pwm_timer, 1, 0xFFFFFFFE);
omap_dm_timer_set_pwm(pwm_timer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_set_load_start(pwm_timer, 1, MOTOR_RESONANCE_COUTER_VALUE);
vibe_timer_state = 1;
}
} else {
if(vibe_timer_state) {
omap_dm_timer_stop(pwm_timer);
omap_dm_timer_disable(pwm_timer);
gpio_set_value(GPIO_VIB_EN, 0);
vibe_timer_state = 0;
}
}
spin_unlock_irqrestore(&vibe__timer_lock, flags);
}
int expire_gptimer12( void )
{
int loop_count;
int callback_result = 0;
//int result;
// egkim [
//omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW );
//omap_dm_timer_set_int_enable( battery_timer, 0 );
//finish_gptimer12(); // Commented on Latona GB
// ]
omap_dm_timer_disable( battery_timer );
//printk("expire_gptimer12 called \n");
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
{
if ( timer_manager[loop_count].remain_time == 0 )
{
//printk(KERN_ERR "call callback function[%s] \n",timer_manager[loop_count].timer.name);
//callback_result = timer_manager[loop_count].timer.expire_callback(&(timer_manager[loop_count].timer));
callback_result = timer_manager[loop_count].timer.expire_callback( timer_manager[loop_count].timer.data );
//result = release_gptimer12(&(timer_manager[loop_count].timer));
//printk("timer release result : %d\n",result);
}
}
}
return callback_result;
}
static ssize_t store_irblaster_freq(struct device *dev, struct device_attribute *attr,
const char* buf, size_t len)
{
frequency = simple_strtol(buf, NULL, 10);
/* Disable pwm */
if (frequency == 0) {
omap_dm_timer_stop(irb_pwm_timer);
omap_dm_timer_disable(irb_pwm_timer);
irb_state = 0;
return 0;
}
/* Enable pwm */
if (irb_state == 0) {
omap_dm_timer_enable(irb_pwm_timer);
omap_dm_timer_set_pwm(irb_pwm_timer, 0, 1, 2);
omap_dm_timer_start(irb_pwm_timer);
irb_state = 1;
}
pwm_set_speed(irb_pwm_timer, frequency, duty_cycle);
return len;
}
/*
* For requesting the "GPtimer#" also for setting the default value in registers
*/
static int vibtonz_ReqGPTimer(void)
{
int ret;
// printk("[VIBRATOR] %s \n",__func__);
gptimer=omap_dm_timer_request_specific(VIBE_GPTIMER_NUM);
if (gptimer == NULL) {
// printk("failed to request pwm timer\n");
ret = -ENODEV;
}
// omap_dm_timer_enable(gptimer);
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_disable(gptimer);
// omap_dm_timer_set_load(gptimer, 1, 0xffffff00);
/*
Change for Interrupt
*/
// omap2_gp_timer_irq.dev_id=(void *)gptimer;
// setup_irq(omap_dm_timer_get_irq(gptimer),&omap2_gp_timer_irq); /* Request for interrupt Number */
// omap_dm_timer_set_int_enable(gptimer,OMAP_TIMER_INT_OVERFLOW);
// omap_dm_timer_set_int_enable(gptimer,OMAP_TIMER_INT_MATCH);
// omap_dm_timer_stop(gptimer);
// omap_dm_timer_disable(gptimer);
return 0;
}
static void sholest_lvibrator_power_off(void)
{
#ifdef CONFIG_VIB_PWM
gpio_set_value(SHOLEST_VIBRATOR_EN_GPIO, 0);
#endif
omap_dm_timer_stop(vib_pwm_timer);
omap_dm_timer_disable(vib_pwm_timer);
}
static void omap_pwm_led_power_off(struct omap_pwm_led *led)
{
if (!led->powered)
return;
led->powered = 0;
/* Everything off */
omap_dm_timer_stop(led->intensity_timer);
omap_dm_timer_disable(led->intensity_timer);
if (led->blink_timer != NULL) {
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_disable(led->blink_timer);
}
if (led->pdata->set_power != NULL)
led->pdata->set_power(led->pdata, 0);
}
static void omap_pwm_led_power_off(struct omap_pwm_led *led)
{
pr_debug("%s%s: \n", PASS1,__func__);
printk("!!!!!!!!!!%s the brightness is %d \n",__func__, led->brightness);
if (!led->powered)
return;
led->powered = 0;
/* Everything off */
omap_dm_timer_set_pwm(led->intensity_timer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_stop(led->intensity_timer);
omap_dm_timer_disable(led->intensity_timer);
if (led->blink_timer != NULL) {
omap_dm_timer_stop(led->blink_timer);
omap_dm_timer_disable(led->blink_timer);
}
if (led->pdata->set_power != NULL)
led->pdata->set_power(led->pdata, 0);
}
void pwm_gpt_stop(int id)
{
if ( !_check_id(id) ) {
return;
}
if ( !_check_timer(id) ) {
return;
}
omap_dm_timer_stop(gpt_pwm_list[id].timer);
omap_dm_timer_disable(gpt_pwm_list[id].timer);
}
static int panel_set_backlight_level(
struct omap_display *disp, int level)
{
int hw_level;
pr_debug("panel_set_backlight_level [%s] %d\n",
disp != NULL ? disp->panel->name: "cpt_wvga_48", level);
/* skip if panel is not on */
if (panel_state == 0) {
saved_bkl_level = level;
return 0;
}
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (bkl_level == level)
return 0;
/* stop backlight? */
if (level == 0) {
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 0);
omap_dm_timer_stop(bkl_pwm);
omap_dm_timer_disable(bkl_pwm);
bkl_level = 0;
return 0;
}
/* start backlight? */
if (bkl_level == 0) {
omap_dm_timer_enable(bkl_pwm);
omap_dm_timer_set_pwm(bkl_pwm, 0, 1, 2);
omap_dm_timer_start(bkl_pwm);
if (GPIO_EXISTS(display_gpio.bkl_pwon))
omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 1);
}
/* set new level, g7 machines have inverted level */
hw_level = level;
if (!machine_is_archos_g6h())
hw_level = 255 - level;
pwm_set_speed(bkl_pwm, 10000, hw_level);
bkl_level = level;
return 0;
}
static void backlight_gptimer_update(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
omap_dm_timer_set_load(lcd->gptimer, 1, -PWM_DUTY_MAX);
omap_dm_timer_set_match(lcd->gptimer, 1, /* 0~25 */
-PWM_DUTY_MAX + lcd->current_brightness);
omap_dm_timer_set_pwm(lcd->gptimer, 0, 1,
OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);
omap_dm_timer_enable(lcd->gptimer);
omap_dm_timer_write_counter(lcd->gptimer, -2);
omap_dm_timer_disable(lcd->gptimer);
omap_dm_timer_start(lcd->gptimer);
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
psSysSpecData->psGPTimer = NULL;
}
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
psSysSpecData->psGPTimer = NULL;
}
}
int init_gptimer12 ( void )
{
gptimer12_count = 0;
memset( &timer_manager, 0, sizeof( timer_manager ) );
battery_timer = omap_dm_timer_request_specific(12);
BUG_ON( battery_timer == NULL );
omap_dm_timer_set_source( battery_timer, OMAP_TIMER_SRC_32_KHZ );
//battery_timer_irq.dev_id = (void *)battery_timer;
//setup_irq(omap_dm_timer_get_irq(battery_timer), &battery_timer_irq);
//omap_dm_timer_set_int_enable(battery_timer, OMAP_TIMER_INT_OVERFLOW);
//omap_dm_timer_set_prescaler(battery_timer, GP_TIMER12_PRESCALAR);
omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW | OMAP_TIMER_INT_CAPTURE
| OMAP_TIMER_INT_MATCH );
omap_dm_timer_disable( battery_timer );
return 0;
}
/*
* Driver Exit
*/
static void __exit hello_exit(void)
{
omap_dm_timer_disable(timer);
omap_dm_timer_free(timer);
/* Release the major number */
unregister_chrdev_region((my_dev_number), 1);
/* Destroy device */
device_destroy (my_dev_class, MKDEV(MAJOR(my_dev_number), 0));
cdev_del(&hrt_devp->cdev);
kfree(hrt_devp);
kfree(timer);
/* Destroy driver_class */
class_destroy(my_dev_class);
printk("My Driver removed.\n");
}
static int panel_set_vcom_level(
struct omap_display *disp, int level)
{
pr_debug("panel_set_vcom_level [%s] %i\n",
disp->panel->name, level);
/* clamp the level */
if (level < 0)
level = 0;
if (level > 255)
level = 255;
/* nothing to do if levels are equal */
if (vcom_level == level)
return 0;
/* stop vcom? */
if (level == 0) {
omap_dm_timer_stop(vcom_pwm);
omap_dm_timer_disable(vcom_pwm);
vcom_level = 0;
return 0;
}
/* start vcom? */
if (vcom_level == 0) {
omap_dm_timer_enable(vcom_pwm);
omap_dm_timer_set_pwm(vcom_pwm, 0, 1, 2);
omap_dm_timer_start(vcom_pwm);
}
vcom_level = level;
pwm_set_speed(vcom_pwm, 10000, vcom_level);
vcom_level = level;
return 0;
}
static int vibrator_probe(struct platform_device *pdev)
{
struct pwm_vib_platform_data *pdata = pdev->dev.platform_data;
struct pwm_vib_data *data;
int ret = 0;
if (!pdata) {
ret = -EBUSY;
goto err0;
}
data = kzalloc(sizeof(struct pwm_vib_data), GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
goto err0;
}
data->pdata = pdata;
INIT_WORK(&data->vibrator_work, update_vibrator);
vibe_timer_state = 0;
hrtimer_init(&data->vibe_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
data->vibe_timer.function = vibrator_timer_func;
spin_lock_init(&data->vibe_lock);
spin_lock_init(&vibe__timer_lock);
data->dev.name = "vibrator";
data->dev.get_time = vibrator_get_time;
data->dev.enable = vibrator_enable;
pwm_timer = omap_dm_timer_request_specific(MOTOR_RESONANCE_TIMER_ID);
if (pwm_timer == NULL) {
pr_err(KERN_ERR "failed to request vibrator pwm timer\n");
goto err1;
}
/* omap_dm_timer_request_specific enables the timer */
// dm timer failed to be disabled.
// omap_dm_timer_disable(pwm_timer);
omap_dm_timer_set_source(pwm_timer, MOTOR_RESONANCE_SRC_CLK);
// dm timer should be disabled here.
omap_dm_timer_disable(pwm_timer);
ret = timed_output_dev_register(&data->dev);
if (ret < 0)
goto err1;
if (data->pdata->init) {
ret = data->pdata->init();
if (ret < 0)
goto err2;
}
gpio_request(GPIO_VIB_EN, "vib_en_gpio");
gpio_direction_output(GPIO_VIB_EN, 1);
gpio_set_value(GPIO_VIB_EN, 0);
misc_data= data;
platform_set_drvdata(pdev, data);
vibrator_enable(&data->dev, data->pdata->initial_vibrate);
pr_info("COSMO vibrator is initialized\n");
return 0;
err2:
timed_output_dev_unregister(&data->dev);
err1:
kfree(data->pdata);
kfree(data);
err0:
return ret;
}
static int _init_gpt(void)
{
int irqno;
int ret = 0;
if ((gpt_pwm_list[IRBLASTER_PWM].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_PWM].no)) == NULL) {
printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no);
return -ENODEV;
}
omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_PWM].timer, gpt_pwm_list[IRBLASTER_PWM].source);
gpt_pwm_list[IRBLASTER_PWM].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_PWM].timer));
printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no, gpt_pwm_list[IRBLASTER_PWM].rate);
if ((gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_TIMER_CTRL].no)) == NULL) {
printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no);
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer);
return -ENODEV;
}
omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, gpt_pwm_list[IRBLASTER_TIMER_CTRL].source);
gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer));
printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no, gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate);
/* select irblaster configuration */
_select_irb_config();
/* enable timer clock */
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
/* set modulation mod */
/* trigger on overflow and match */
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2);
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 0, 1, 2);
//if ( gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config )
// omap_cfg_reg(gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config);
irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
if (request_irq(irqno, omap2_irblaster_timer_interrupt,
IRQF_DISABLED, "gp timer", NULL)) {
ret = -EBUSY;
goto failed_request_irq;
}
omap_dm_timer_set_int_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, IRBLASTER_TIMER_CTRL_IT_TYPE);
/* disable timer clocks after init */
omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_PWM].timer);
init_waitqueue_head(&irb_wait);
_gio_debug_init();
return 0;
failed_request_irq:
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
return ret;
}
static void sholest_lvibrator_exit(void)
{
omap_dm_timer_stop(vib_pwm_timer);
omap_dm_timer_disable(vib_pwm_timer);
}
/*
* ======== WMD_DEH_Create ========
* Creates DEH manager object.
*/
DSP_STATUS WMD_DEH_Create(OUT struct DEH_MGR **phDehMgr,
struct DEV_OBJECT *hDevObject)
{
DSP_STATUS status = DSP_SOK;
struct DEH_MGR *pDehMgr = NULL;
struct CFG_HOSTRES cfgHostRes;
struct CFG_DEVNODE *hDevNode;
struct WMD_DEV_CONTEXT *hWmdContext = NULL;
/* Message manager will be created when a file is loaded, since
* size of message buffer in shared memory is configurable in
* the base image. */
/* Get WMD context info. */
DEV_GetWMDContext(hDevObject, &hWmdContext);
DBC_Assert(hWmdContext);
dummyVaAddr = 0;
/* Allocate IO manager object: */
MEM_AllocObject(pDehMgr, struct DEH_MGR, SIGNATURE);
if (pDehMgr == NULL) {
status = DSP_EMEMORY;
} else {
/* Create an NTFY object to manage notifications */
status = NTFY_Create(&pDehMgr->hNtfy);
/* Create a MMUfault DPC */
tasklet_init(&pDehMgr->dpc_tasklet, MMU_FaultDpc, (u32)pDehMgr);
if (DSP_SUCCEEDED(status))
status = DEV_GetDevNode(hDevObject, &hDevNode);
if (DSP_SUCCEEDED(status))
status = CFG_GetHostResources(hDevNode, &cfgHostRes);
if (DSP_SUCCEEDED(status)) {
/* Fill in context structure */
pDehMgr->hWmdContext = hWmdContext;
pDehMgr->errInfo.dwErrMask = 0L;
pDehMgr->errInfo.dwVal1 = 0L;
pDehMgr->errInfo.dwVal2 = 0L;
pDehMgr->errInfo.dwVal3 = 0L;
/* Install ISR function for DSP MMU fault */
if ((request_irq(INT_DSP_MMU_IRQ, MMU_FaultIsr, 0,
"DspBridge\tiommu fault", (void *)pDehMgr)) == 0)
status = DSP_SOK;
else
status = DSP_EFAIL;
}
}
if (DSP_FAILED(status)) {
/* If create failed, cleanup */
WMD_DEH_Destroy((struct DEH_MGR *)pDehMgr);
*phDehMgr = NULL;
} else {
timer = omap_dm_timer_request_specific(
GPTIMER_FOR_DSP_MMU_FAULT);
if (timer)
omap_dm_timer_disable(timer);
else {
pr_err("%s:GPTimer not available\n", __func__);
return -ENODEV;
}
*phDehMgr = (struct DEH_MGR *)pDehMgr;
}
return status;
}
/*
* ======== WMD_DEH_Notify ========
* DEH error notification function. Informs user about the error.
*/
void WMD_DEH_Notify(struct DEH_MGR *hDehMgr, u32 ulEventMask,
u32 dwErrInfo)
{
struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr;
struct WMD_DEV_CONTEXT *pDevContext;
u32 memPhysical = 0;
u32 HW_MMU_MAX_TLB_COUNT = 31;
extern u32 faultAddr;
u32 cnt = 0;
if (MEM_IsValidHandle(pDehMgr, SIGNATURE)) {
printk(KERN_INFO "WMD_DEH_Notify: ********** DEVICE EXCEPTION "
"**********\n");
pDevContext = (struct WMD_DEV_CONTEXT *)pDehMgr->hWmdContext;
switch (ulEventMask) {
case DSP_SYSERROR:
/* reset errInfo structure before use */
pDehMgr->errInfo.dwErrMask = DSP_SYSERROR;
pDehMgr->errInfo.dwVal1 = 0L;
pDehMgr->errInfo.dwVal2 = 0L;
pDehMgr->errInfo.dwVal3 = 0L;
pDehMgr->errInfo.dwVal1 = dwErrInfo;
printk(KERN_ERR "WMD_DEH_Notify: DSP_SYSERROR, errInfo "
"= 0x%x\n", dwErrInfo);
dump_dl_modules(pDevContext);
dump_dsp_stack(pDevContext);
break;
case DSP_MMUFAULT:
/* MMU fault routine should have set err info
* structure */
pDehMgr->errInfo.dwErrMask = DSP_MMUFAULT;
printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT,"
"errInfo = 0x%x\n", dwErrInfo);
printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, High "
"Address = 0x%x\n",
(unsigned int)pDehMgr->errInfo.dwVal1);
printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, Low "
"Address = 0x%x\n",
(unsigned int)pDehMgr->errInfo.dwVal2);
printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, fault "
"address = 0x%x\n", (unsigned int)faultAddr);
PrintDspTraceBuffer(pDevContext);
dump_dl_modules(pDevContext);
dummyVaAddr = (u32)MEM_Calloc(sizeof(char) * 0x1000,
MEM_PAGED);
memPhysical = VirtToPhys(PG_ALIGN_LOW((u32)dummyVaAddr,
PG_SIZE_4K));
pDevContext = (struct WMD_DEV_CONTEXT *)
pDehMgr->hWmdContext;
/* Reset the dynamic mmu index to fixed count if it
* exceeds 31. So that the dynmmuindex is always
* between the range of standard/fixed entries
* and 31. */
if (pDevContext->numTLBEntries >
HW_MMU_MAX_TLB_COUNT) {
pDevContext->numTLBEntries = pDevContext->
fixedTLBEntries;
}
HW_MMU_TLBAdd(pDevContext->dwDSPMmuBase,
memPhysical, faultAddr, HW_PAGE_SIZE_4KB, 1,
&mapAttrs, HW_SET, HW_SET);
/*
* Send a GP Timer interrupt to DSP
* The DSP expects a GP timer interrupt after an
* MMU-Fault Request GPTimer
*/
if (timer) {
omap_dm_timer_enable(timer);
/* Enable overflow interrupt */
omap_dm_timer_set_int_enable(timer,
GPTIMER_IRQ_OVERFLOW);
/*
* Set counter value to overflow counter after
* one tick and start timer
*/
omap_dm_timer_set_load_start(timer, 0,
0xfffffffe);
/* Wait 80us for timer to overflow */
udelay(80);
/* Check interrupt status and */
/* wait for interrupt */
cnt = 0;
while (!(omap_dm_timer_read_status(timer) &
GPTIMER_IRQ_OVERFLOW)) {
if (cnt++ >=
GPTIMER_IRQ_WAIT_MAX_CNT) {
pr_err("%s: GPTimer interrupt"
" failed\n", __func__);
break;
}
}
}
/* Clear MMU interrupt */
HW_MMU_EventAck(pDevContext->dwDSPMmuBase,
HW_MMU_TRANSLATION_FAULT);
dump_dsp_stack(hDehMgr->hWmdContext);
if (timer)
omap_dm_timer_disable(timer);
break;
#ifdef CONFIG_BRIDGE_NTFY_PWRERR
case DSP_PWRERROR:
/* reset errInfo structure before use */
pDehMgr->errInfo.dwErrMask = DSP_PWRERROR;
pDehMgr->errInfo.dwVal1 = 0L;
pDehMgr->errInfo.dwVal2 = 0L;
pDehMgr->errInfo.dwVal3 = 0L;
pDehMgr->errInfo.dwVal1 = dwErrInfo;
printk(KERN_ERR "WMD_DEH_Notify: DSP_PWRERROR, errInfo "
"= 0x%x\n", dwErrInfo);
break;
#endif /* CONFIG_BRIDGE_NTFY_PWRERR */
#ifdef CONFIG_BRIDGE_WDT3
case DSP_WDTOVERFLOW:
pDehMgr->errInfo.dwErrMask = DSP_WDTOVERFLOW;
pDehMgr->errInfo.dwVal1 = 0L;
pDehMgr->errInfo.dwVal2 = 0L;
pDehMgr->errInfo.dwVal3 = 0L;
pr_err("WMD_DEH_Notify: DSP_WDTOVERFLOW \n ");
break;
#endif
default:
DBG_Trace(DBG_LEVEL6,
"WMD_DEH_Notify: Unknown Error, errInfo = "
"0x%x\n", dwErrInfo);
break;
}
/* Filter subsequent notifications when an error occurs */
if (pDevContext->dwBrdState != BRD_ERROR) {
NTFY_Notify(pDehMgr->hNtfy, ulEventMask);
#ifdef CONFIG_BRIDGE_RECOVERY
bridge_recover_schedule();
#endif
}
/* Set the Board state as ERROR */
pDevContext->dwBrdState = BRD_ERROR;
/* Disable all the clocks that were enabled by DSP */
(void)DSP_PeripheralClocks_Disable(pDevContext, NULL);
#ifdef CONFIG_BRIDGE_WDT3
/*
* Avoid the subsequent WDT if it happens once,
* also If MMU fault occurs
*/
dsp_wdt_enable(false);
#endif
}
}
static int omap_pwm_led_probe(struct platform_device *pdev)
{
struct omap_pwm_led_platform_data *pdata = pdev->dev.platform_data;
struct omap_pwm_led *led;
int ret;
led = kzalloc(sizeof(struct omap_pwm_led), GFP_KERNEL);
if (led == NULL) {
dev_err(&pdev->dev, "No memory for device\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, led);
led->cdev.brightness_set = omap_pwm_led_set;
led->cdev.default_trigger = pdata->default_trigger;
led->cdev.name = pdata->name;
led->pdata = pdata;
led->brightness = LED_OFF;
INIT_WORK(&led->work, omap_pwm_led_work);
dev_info(&pdev->dev, "OMAP PWM LED (%s) at GP timer %d/%d\n",
pdata->name, pdata->intensity_timer, pdata->blink_timer);
/* register our new led device */
ret = led_classdev_register(&pdev->dev, &led->cdev);
if (ret < 0) {
dev_err(&pdev->dev, "led_classdev_register failed\n");
goto error_classdev;
}
/* get related dm timers */
led->intensity_timer = omap_dm_timer_request_specific(pdata->intensity_timer);
if (led->intensity_timer == NULL) {
dev_err(&pdev->dev, "failed to request intensity pwm timer\n");
ret = -ENODEV;
goto error_intensity;
}
omap_pwm_led_set(&led->cdev, led->brightness);
omap_dm_timer_disable(led->intensity_timer);
if (pdata->blink_timer != 0) {
led->blink_timer = omap_dm_timer_request_specific(pdata->blink_timer);
if (led->blink_timer == NULL) {
dev_err(&pdev->dev, "failed to request blinking pwm timer\n");
ret = -ENODEV;
goto error_blink1;
}
omap_dm_timer_disable(led->blink_timer);
ret = device_create_file(led->cdev.dev,
&dev_attr_on_period);
if(ret)
goto error_blink2;
ret = device_create_file(led->cdev.dev,
&dev_attr_off_period);
if(ret)
goto error_blink3;
}
return 0;
error_blink3:
device_remove_file(led->cdev.dev,
&dev_attr_on_period);
error_blink2:
dev_err(&pdev->dev, "failed to create device file(s)\n");
error_blink1:
omap_dm_timer_free(led->intensity_timer);
error_intensity:
led_classdev_unregister(&led->cdev);
error_classdev:
kfree(led);
return ret;
}
/*
* Release dmtimer
* TESTED
*/
void HRTDriver_release_timer(struct omap_dm_timer *timer) {
omap_dm_timer_disable(timer);
omap_dm_timer_free(timer);
}
/*
* ======== bridge_deh_notify ========
* DEH error notification function. Informs user about the error.
*/
void bridge_deh_notify(struct deh_mgr *hdeh_mgr, u32 ulEventMask, u32 dwErrInfo)
{
struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)hdeh_mgr;
struct wmd_dev_context *dev_context;
int status = 0;
u32 mem_physical = 0;
u32 hw_mmu_max_tlb_count = 31;
extern u32 fault_addr;
struct cfg_hostres *resources;
hw_status hw_status_obj;
u32 cnt = 0;
if (deh_mgr_obj) {
printk(KERN_INFO
"bridge_deh_notify: ********** DEVICE EXCEPTION "
"**********\n");
dev_context =
(struct wmd_dev_context *)deh_mgr_obj->hwmd_context;
resources = dev_context->resources;
switch (ulEventMask) {
case DSP_SYSERROR:
/* reset err_info structure before use */
deh_mgr_obj->err_info.dw_err_mask = DSP_SYSERROR;
deh_mgr_obj->err_info.dw_val1 = 0L;
deh_mgr_obj->err_info.dw_val2 = 0L;
deh_mgr_obj->err_info.dw_val3 = 0L;
deh_mgr_obj->err_info.dw_val1 = dwErrInfo;
printk(KERN_ERR
"bridge_deh_notify: DSP_SYSERROR, err_info "
"= 0x%x\n", dwErrInfo);
dump_dl_modules(dev_context);
dump_dsp_stack(dev_context);
break;
case DSP_MMUFAULT:
/* MMU fault routine should have set err info
* structure */
deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT;
printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT,"
"err_info = 0x%x\n", dwErrInfo);
printk(KERN_INFO
"bridge_deh_notify: DSP_MMUFAULT, High "
"Address = 0x%x\n",
(unsigned int)deh_mgr_obj->err_info.dw_val1);
printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT, Low "
"Address = 0x%x\n",
(unsigned int)deh_mgr_obj->err_info.dw_val2);
printk(KERN_INFO
"bridge_deh_notify: DSP_MMUFAULT, fault "
"address = 0x%x\n", (unsigned int)fault_addr);
dummy_va_addr = (u32) kzalloc(sizeof(char) * 0x1000,
GFP_ATOMIC);
mem_physical =
VIRT_TO_PHYS(PG_ALIGN_LOW
((u32) dummy_va_addr, PG_SIZE4K));
dev_context = (struct wmd_dev_context *)
deh_mgr_obj->hwmd_context;
print_dsp_trace_buffer(dev_context);
dump_dl_modules(dev_context);
/* Reset the dynamic mmu index to fixed count if it
* exceeds 31. So that the dynmmuindex is always
* between the range of standard/fixed entries
* and 31. */
if (dev_context->num_tlb_entries >
hw_mmu_max_tlb_count) {
dev_context->num_tlb_entries =
dev_context->fixed_tlb_entries;
}
if (DSP_SUCCEEDED(status)) {
hw_status_obj =
hw_mmu_tlb_add(resources->dw_dmmu_base,
mem_physical, fault_addr,
HW_PAGE_SIZE4KB, 1,
&map_attrs, HW_SET, HW_SET);
}
/*
* Send a GP Timer interrupt to DSP
* The DSP expects a GP timer interrupt after an
* MMU-Fault Request GPTimer
*/
if (timer) {
omap_dm_timer_enable(timer);
/* Enable overflow interrupt */
omap_dm_timer_set_int_enable(timer,
GPTIMER_IRQ_OVERFLOW);
/*
* Set counter value to overflow counter after
* one tick and start timer
*/
omap_dm_timer_set_load_start(timer, 0,
0xfffffffe);
/* Wait 80us for timer to overflow */
udelay(80);
/*
* Check interrupt status and
* wait for interrupt
*/
cnt = 0;
while (!(omap_dm_timer_read_status(timer) &
GPTIMER_IRQ_OVERFLOW)) {
if (cnt++ >=
GPTIMER_IRQ_WAIT_MAX_CNT) {
pr_err("%s: GPTimer interrupt"
" failed\n", __func__);
break;
}
}
}
/* Clear MMU interrupt */
hw_mmu_event_ack(resources->dw_dmmu_base,
HW_MMU_TRANSLATION_FAULT);
dump_dsp_stack(deh_mgr_obj->hwmd_context);
if (timer)
omap_dm_timer_disable(timer);
break;
#ifdef CONFIG_BRIDGE_NTFY_PWRERR
case DSP_PWRERROR:
/* reset err_info structure before use */
deh_mgr_obj->err_info.dw_err_mask = DSP_PWRERROR;
deh_mgr_obj->err_info.dw_val1 = 0L;
deh_mgr_obj->err_info.dw_val2 = 0L;
deh_mgr_obj->err_info.dw_val3 = 0L;
deh_mgr_obj->err_info.dw_val1 = dwErrInfo;
printk(KERN_ERR
"bridge_deh_notify: DSP_PWRERROR, err_info "
"= 0x%x\n", dwErrInfo);
break;
#endif /* CONFIG_BRIDGE_NTFY_PWRERR */
#ifdef CONFIG_BRIDGE_WDT3
case DSP_WDTOVERFLOW:
deh_mgr_obj->err_info.dw_err_mask = DSP_WDTOVERFLOW;
deh_mgr_obj->err_info.dw_val1 = 0L;
deh_mgr_obj->err_info.dw_val2 = 0L;
deh_mgr_obj->err_info.dw_val3 = 0L;
pr_err("bridge_deh_notify: DSP_WDTOVERFLOW\n ");
break;
#endif
default:
dev_dbg(bridge, "%s: Unknown Error, err_info = 0x%x\n",
__func__, dwErrInfo);
break;
}
/* Filter subsequent notifications when an error occurs */
if (dev_context->dw_brd_state != BRD_ERROR) {
ntfy_notify(deh_mgr_obj->ntfy_obj, ulEventMask);
#ifdef CONFIG_BRIDGE_RECOVERY
bridge_recover_schedule();
#endif
}
/* Set the Board state as ERROR */
dev_context->dw_brd_state = BRD_ERROR;
/* Disable all the clocks that were enabled by DSP */
(void)dsp_peripheral_clocks_disable(dev_context, NULL);
#ifdef CONFIG_BRIDGE_WDT3
/*
* Avoid the subsequent WDT if it happens once,
* also If MMU fault occurs
*/
dsp_wdt_enable(false);
#endif
}
}
int release_gptimer12(struct gptimer12_timer *timer)
{
int loop_count;
int temp_count;
int slot = -1;
unsigned int next_time=0;
int current_time;
if ( gptimer12_count == 0 )
return -1;
//printk ("\ntest 1 timer_instance_count : %d \n",gptimer12_count);
for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL)
{
if( strcmp( timer->name, timer_manager[loop_count].timer.name ) == 0 )
{
slot = loop_count;
break;
}
}
}
if ( slot == -1 )
return -1;
// case : delete current working timer
//CM_ICLKEN_WKUP |= 1 << 1;
cm_val = cm_read_mod_reg( WKUP_MOD, CM_ICLKEN1 );
cm_val = cm_val | ( 1 << 1 );
cm_write_mod_reg( cm_val, WKUP_MOD, CM_ICLKEN1 );
if ( timer_manager[slot].remain_time == 0 )
{
//current timer ..
omap_dm_timer_stop( battery_timer );
current_time = GP_TIMER12_TICK_TO_SEC( 0xffffffff - omap_dm_timer_read_counter( battery_timer ) );
//printk("test1 current_time : %d\n",current_time);
for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ )
{
timer_manager[loop_count].remain_time += current_time;
#if 0
if((timer_manager[loop_count].timer.name) != 0)
{
if((timer_manager[loop_count].remain_time) == 0)
timer_manager[loop_count].remain_time = current_time;
}
#endif
}
}
memset ( &( timer_manager[slot] ), 0, sizeof( struct gptimer12_manager ) );
gptimer12_count--;
if( gptimer12_count < 0 )
gptimer12_count = 0;
//printk("released : timer_instance_count : %d\n",gptimer12_count);
if ( gptimer12_count == 0 )
{
//printk("\n\n M timer empty .. \n");
prcm_wakeup_event_control( PRCM_GPT12, PRCM_DISABLE ); //egkim
finish_gptimer12(); //egkim
omap_dm_timer_disable( battery_timer );
//CM_ICLKEN_WKUP &= ~(1 << 1);
cm_val = cm_read_mod_reg( WKUP_MOD, CM_ICLKEN1 );
cm_val = cm_val & ~( 1 << 1 );
cm_write_mod_reg( cm_val, WKUP_MOD,CM_ICLKEN1 );
/* change active state. */
timer->active = false;
return 0;
}
for ( temp_count = 0 ; temp_count < MAX_GPTIMER12_INSTANCE ; temp_count++ )
{
if( timer_manager[temp_count].timer.name != NULL )
{
next_time = timer_manager[temp_count].remain_time;
break;
}
}
for ( temp_count = 0 ; temp_count < MAX_GPTIMER12_INSTANCE ; temp_count++ )
{
if ( timer_manager[temp_count].timer.name != NULL )
{
next_time = timer_manager[temp_count].remain_time;
break;
}
}
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if( timer_manager[loop_count].timer.name != NULL )
{
if ( next_time > timer_manager[loop_count].remain_time )
next_time = timer_manager[loop_count].remain_time;
}
}
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if( timer_manager[loop_count].timer.name != NULL )
timer_manager[loop_count].remain_time -= next_time;
}
printk( "\n\n\n next timeout : %d\n",next_time );
prcm_wakeup_event_control( PRCM_GPT12, PRCM_ENABLE );
omap_dm_timer_set_load_start( battery_timer, 0, 0xffffffff - GP_TIMER12_SEC_TO_TICK(next_time) );
//CM_ICLKEN_WKUP &= ~(1 << 1);
cm_val = cm_read_mod_reg( WKUP_MOD, CM_ICLKEN1 );
cm_val = cm_val & ~( 1 << 1 );
cm_write_mod_reg( cm_val, WKUP_MOD,CM_ICLKEN1 );
timer->active = false;
return 0;
}
static void backlight_gptimer_stop(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
omap_dm_timer_disable(lcd->gptimer);
}
/*
* ======== bridge_deh_create ========
* Creates DEH manager object.
*/
int bridge_deh_create(OUT struct deh_mgr **phDehMgr,
struct dev_object *hdev_obj)
{
int status = 0;
struct deh_mgr *deh_mgr_obj = NULL;
struct wmd_dev_context *hwmd_context = NULL;
/* Message manager will be created when a file is loaded, since
* size of message buffer in shared memory is configurable in
* the base image. */
/* Get WMD context info. */
dev_get_wmd_context(hdev_obj, &hwmd_context);
DBC_ASSERT(hwmd_context);
dummy_va_addr = 0;
/* Allocate IO manager object: */
deh_mgr_obj = kzalloc(sizeof(struct deh_mgr), GFP_KERNEL);
if (deh_mgr_obj == NULL) {
status = -ENOMEM;
} else {
/* Create an NTFY object to manage notifications */
deh_mgr_obj->ntfy_obj = kmalloc(sizeof(struct ntfy_object),
GFP_KERNEL);
if (deh_mgr_obj->ntfy_obj)
ntfy_init(deh_mgr_obj->ntfy_obj);
else
status = -ENOMEM;
deh_mgr_obj->mmu_wq = create_workqueue("dsp-mmu_wq");
if (!deh_mgr_obj->mmu_wq)
status = -ENOMEM;
INIT_WORK(&deh_mgr_obj->fault_work, mmu_fault_work);
if (DSP_SUCCEEDED(status)) {
/* Fill in context structure */
deh_mgr_obj->hwmd_context = hwmd_context;
deh_mgr_obj->err_info.dw_err_mask = 0L;
deh_mgr_obj->err_info.dw_val1 = 0L;
deh_mgr_obj->err_info.dw_val2 = 0L;
deh_mgr_obj->err_info.dw_val3 = 0L;
/* Install ISR function for DSP MMU fault */
if ((request_irq(INT_DSP_MMU_IRQ, mmu_fault_isr, 0,
"DspBridge\tiommu fault",
(void *)deh_mgr_obj)) == 0)
status = 0;
else
status = -EPERM;
}
}
if (DSP_FAILED(status)) {
/* If create failed, cleanup */
bridge_deh_destroy((struct deh_mgr *)deh_mgr_obj);
*phDehMgr = NULL;
} else {
timer = omap_dm_timer_request_specific(
GPTIMER_FOR_DSP_MMU_FAULT);
if (timer)
omap_dm_timer_disable(timer);
else {
pr_err("%s:GPTimer not available\n", __func__);
return -ENODEV;
}
*phDehMgr = (struct deh_mgr *)deh_mgr_obj;
}
return status;
}
