static int lirc_rx51_free_port(struct lirc_rx51 *lirc_rx51)
{
omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
free_irq(lirc_rx51->irq_num, lirc_rx51);
lirc_rx51_off(lirc_rx51);
omap_dm_timer_disable(lirc_rx51->pwm_timer);
omap_dm_timer_disable(lirc_rx51->pulse_timer);
omap_dm_timer_free(lirc_rx51->pwm_timer);
omap_dm_timer_free(lirc_rx51->pulse_timer);
lirc_rx51->wbuf_index = -1;
return 0;
}
static int irblaster_remove(struct platform_device *pdev)
{
int irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
free_irq(irqno, NULL);
misc_deregister(&irblast_miscdev);
_select_default_config();
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
return 0;
}
static void gptimer_stop(void)
{
omap_dm_timer_set_int_enable(gptimer, 0);
free_irq(omap_dm_timer_get_irq(gptimer), NULL);
omap_dm_timer_free(gptimer);
gptimer = NULL;
}
static int gptimer_start(void)
{
int err;
u32 count = counter_config[0].count;
BUG_ON(gptimer != NULL);
/* First try to request timers from CORE power domain for OMAP3 */
if (cpu_is_omap34xx()) {
gptimer = omap_dm_timer_request_specific(10);
if (gptimer == NULL)
gptimer = omap_dm_timer_request_specific(11);
}
/* Just any timer would be fine */
if (gptimer == NULL)
gptimer = omap_dm_timer_request();
if (gptimer == NULL)
return -ENODEV;
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
err = request_irq(omap_dm_timer_get_irq(gptimer), gptimer_interrupt,
IRQF_DISABLED, "oprofile gptimer", NULL);
if (err) {
omap_dm_timer_free(gptimer);
gptimer = NULL;
printk(KERN_ERR "oprofile: unable to request gptimer IRQ\n");
return err;
}
if (count < 1)
count = 1;
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - count);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
return 0;
}
/*
* ======== bridge_deh_destroy ========
* Destroys DEH manager object.
*/
int bridge_deh_destroy(struct deh_mgr *hdeh_mgr)
{
int status = 0;
struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)hdeh_mgr;
if (deh_mgr_obj) {
/* Release dummy VA buffer */
bridge_deh_release_dummy_mem();
/* If notification object exists, delete it */
if (deh_mgr_obj->ntfy_obj) {
(void)ntfy_delete(deh_mgr_obj->ntfy_obj);
kfree(deh_mgr_obj->ntfy_obj);
}
/* Disable DSP MMU fault */
free_irq(INT_DSP_MMU_IRQ, deh_mgr_obj);
destroy_workqueue(deh_mgr_obj->mmu_wq);
/* Deallocate the DEH manager object */
kfree(deh_mgr_obj);
/* The GPTimer is no longer needed */
omap_dm_timer_free(timer);
timer = NULL;
}
return status;
}
static int backlight_gptimer_init(struct omap_dss_device *dssdev)
{
struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev);
int ret;
pr_info("(%s): called (@%d)\n", __func__, __LINE__);
if (lcd->pdata->set_gptimer_idle)
lcd->pdata->set_gptimer_idle();
lcd->gptimer =
omap_dm_timer_request_specific(lcd->pdata->backlight_gptimer_num);
if (lcd->gptimer == NULL) {
pr_err("failed to request pwm timer\n");
ret = -ENODEV;
goto err_dm_timer_request;
}
ret = omap_dm_timer_set_source(lcd->gptimer, OMAP_TIMER_SRC_SYS_CLK);
if (ret < 0)
goto err_dm_timer_src;
return ret;
err_dm_timer_src:
omap_dm_timer_free(lcd->gptimer);
lcd->gptimer = NULL;
err_dm_timer_request:
return ret;
}
/*
* ======== WMD_DEH_Destroy ========
* Destroys DEH manager object.
*/
DSP_STATUS WMD_DEH_Destroy(struct DEH_MGR *hDehMgr)
{
DSP_STATUS status = DSP_SOK;
struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr;
if (MEM_IsValidHandle(pDehMgr, SIGNATURE)) {
/* Release dummy VA buffer */
WMD_DEH_ReleaseDummyMem();
/* If notification object exists, delete it */
if (pDehMgr->hNtfy)
(void)NTFY_Delete(pDehMgr->hNtfy);
/* Disable DSP MMU fault */
free_irq(INT_DSP_MMU_IRQ, pDehMgr);
/* Free DPC object */
tasklet_kill(&pDehMgr->dpc_tasklet);
/* Deallocate the DEH manager object */
MEM_FreeObject(pDehMgr);
/* The GPTimer is no longer needed */
if (timer) {
omap_dm_timer_free(timer);
timer = NULL;
}
}
return status;
}
static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51)
{
struct clk *clk_fclk;
int retval, pwm_timer = lirc_rx51->pwm_timer_num;
lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer);
if (lirc_rx51->pwm_timer == NULL) {
dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n",
pwm_timer);
return -EBUSY;
}
lirc_rx51->pulse_timer = omap_dm_timer_request();
if (lirc_rx51->pulse_timer == NULL) {
dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n");
retval = -EBUSY;
goto err1;
}
omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_set_source(lirc_rx51->pulse_timer,
OMAP_TIMER_SRC_SYS_CLK);
omap_dm_timer_enable(lirc_rx51->pwm_timer);
omap_dm_timer_enable(lirc_rx51->pulse_timer);
lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer);
retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler,
IRQF_DISABLED | IRQF_SHARED,
"lirc_pulse_timer", lirc_rx51);
if (retval) {
dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n");
goto err2;
}
clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer);
lirc_rx51->fclk_khz = clk_fclk->rate / 1000;
return 0;
err2:
omap_dm_timer_free(lirc_rx51->pulse_timer);
err1:
omap_dm_timer_free(lirc_rx51->pwm_timer);
return retval;
}
static inline int omap_rproc_start(struct rproc *rproc, u64 bootaddr)
{
struct device *dev = rproc->dev;
struct platform_device *pdev = to_platform_device(dev);
struct omap_rproc_pdata *pdata = dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
struct omap_rproc_priv *rpp = rproc->priv;
int i;
int ret = 0;
if (rproc->secure_mode) {
rproc->secure_reset = true;
ret = rproc_drm_invoke_service(rproc->secure_mode);
if (ret) {
dev_err(rproc->dev, "rproc_drm_invoke_service failed "
"for secure_enable ret = 0x%x\n", ret);
return -ENXIO;
}
}
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
ret = _init_pm_flags(rproc);
if (ret)
return ret;
#endif
for (i = 0; i < pdata->timers_cnt; i++) {
timers[i].odt = omap_dm_timer_request_specific(timers[i].id);
if (!timers[i].odt) {
ret = -EBUSY;
goto out;
}
omap_dm_timer_set_source(timers[i].odt, OMAP_TIMER_SRC_SYS_CLK);
#ifdef CONFIG_REMOTEPROC_WATCHDOG
/* GPT 9 & 11 (ipu); GPT 6 (dsp) are used as watchdog timers */
if ((!strcmp(rproc->name, "dsp") && timers[i].id == 6) ||
(!strcmp(rproc->name, "ipu") &&
(timers[i].id == DUCATI_WDT_TIMER_1 || timers[i].id == DUCATI_WDT_TIMER_2))) {
ret = request_irq(omap_dm_timer_get_irq(timers[i].odt),
omap_rproc_watchdog_isr, IRQF_DISABLED,
"rproc-wdt", rproc);
/* Clean counter, remoteproc proc will set the value */
omap_dm_timer_set_load(timers[i].odt, 0, 0);
}
#endif
}
rpp->bootaddr = bootaddr;
ret = omap_device_enable(pdev);
out:
if (ret) {
while (i--) {
omap_dm_timer_free(timers[i].odt);
timers[i].odt = NULL;
}
}
return ret;
}
static int omap_pwm_led_remove(struct platform_device *pdev)
{
struct omap_pwm_led *led = pdev_to_omap_pwm_led(pdev);
device_remove_file(led->cdev.dev,
&dev_attr_on_period);
device_remove_file(led->cdev.dev,
&dev_attr_off_period);
led_classdev_unregister(&led->cdev);
omap_pwm_led_set(&led->cdev, LED_OFF);
if (led->blink_timer != NULL)
omap_dm_timer_free(led->blink_timer);
omap_dm_timer_free(led->intensity_timer);
kfree(led);
return 0;
}
static void __exit gptimer_request_exit(void)
{
/*Stop the timer*/
omap_dm_timer_stop(timer_ptr);
/*Release the timer*/
omap_dm_timer_free(timer_ptr);
printk(KERN_INFO "GP Timer finalized and stoped\n");
}
// Cleanup after ourselfs
static void __exit gptimer_test_exit(void)
{
printk("gptimer test: cleanup called\n");
// stop the timer
omap_dm_timer_stop(timer_ptr);
// release the IRQ handler
free_irq(timer_irq, timer_irq_handler);
// release the timer
omap_dm_timer_free(timer_ptr);
}
static void __exit pwm_end(void) {
printk(KERN_INFO "Exiting PWM Module. \n");
// stop the timer
omap_dm_timer_stop(timer_ptr);
// release the IRQ handler
free_irq(timer_irq, timer_irq_handler);
// release the timer
omap_dm_timer_free(timer_ptr);
// release GPIO
gpio_free(pwm_data_ptr.pin);
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
psSysSpecData->psGPTimer = NULL;
}
}
/*!
******************************************************************************
@Function ReleaseGPTimer
@Description Release a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
if (psSysSpecData->psGPTimer != NULL)
{
/* Always returns 0 */
(void) omap_dm_timer_stop(psSysSpecData->psGPTimer);
omap_dm_timer_disable(psSysSpecData->psGPTimer);
omap_dm_timer_free(psSysSpecData->psGPTimer);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase.uiAddr = 0;
#endif
psSysSpecData->psGPTimer = NULL;
}
}
/*
* ======== dsp_clk_disable ========
* Purpose:
* Disable the clock.
*
*/
int dsp_clk_disable(enum dsp_clk_id clk_id)
{
int status = 0;
if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
goto out;
}
switch (get_clk_type(clk_id)) {
case IVA2_CLK:
clk_disable(iva2_clk);
break;
case GPT_CLK:
omap_dm_timer_free(timer[clk_id - 1]);
break;
#ifdef CONFIG_OMAP_MCBSP
case MCBSP_CLK:
mcbsp_clk_prepare(false, clk_id);
omap_mcbsp_free(MCBSP_ID(clk_id));
break;
#endif
case WDT_CLK:
dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
break;
case SSI_CLK:
ssi_clk_prepare(false);
ssi_clk_prepare(false);
clk_disable(ssi.sst_fck);
clk_disable(ssi.ssr_fck);
clk_disable(ssi.ick);
break;
default:
dev_err(bridge, "Invalid clock id for disable\n");
status = -EPERM;
}
if (!status)
set_dsp_clk_inactive(&dsp_clocks, clk_id);
out:
return status;
}
/*
* Driver Exit
*/
static void __exit hello_exit(void)
{
omap_dm_timer_disable(timer);
omap_dm_timer_free(timer);
/* Release the major number */
unregister_chrdev_region((my_dev_number), 1);
/* Destroy device */
device_destroy (my_dev_class, MKDEV(MAJOR(my_dev_number), 0));
cdev_del(&hrt_devp->cdev);
kfree(hrt_devp);
kfree(timer);
/* Destroy driver_class */
class_destroy(my_dev_class);
printk("My Driver removed.\n");
}
static inline int proc44x_stop(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct omap_rproc *obj = (struct omap_rproc *)platform_get_drvdata(
to_platform_device(dev));
int ret = 0;
if (obj->state == OMAP_RPROC_RUNNING) {
ret = omap_device_shutdown(pdev);
if (ret)
dev_err(dev, "%s err 0x%x\n", __func__, ret);
if (obj->dmtimer) {
omap_dm_timer_free(obj->dmtimer);
obj->dmtimer = NULL;
}
}
obj->state = OMAP_RPROC_STOPPED;
return ret;
}
static inline int omap_rproc_stop(struct rproc *rproc)
{
struct device *dev = rproc->dev;
struct platform_device *pdev = to_platform_device(dev);
struct omap_rproc_pdata *pdata = dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
int ret, i;
#ifdef CONFIG_REMOTE_PROC_AUTOSUSPEND
_destroy_pm_flags(rproc);
#endif
if (rproc->secure_reset) {
ret = rproc_drm_invoke_service(false);
if (ret)
dev_err(rproc->dev, "rproc_drm_invoke_service failed "
"for secure disable ret = 0x%x\n", ret);
rproc->secure_reset = false;
}
ret = omap_device_idle(pdev);
if (ret)
goto err;
for (i = 0; i < pdata->timers_cnt; i++) {
#ifdef CONFIG_REMOTEPROC_WATCHDOG
/* GPT 9 & 11 (ipu); GPT 6 (dsp) are used as watchdog timers */
if ((!strcmp(rproc->name, "dsp") && timers[i].id == 6) ||
(!strcmp(rproc->name, "ipu") &&
(timers[i].id == DUCATI_WDT_TIMER_1 || timers[i].id == DUCATI_WDT_TIMER_2)))
free_irq(omap_dm_timer_get_irq(timers[i].odt), rproc);
#endif
omap_dm_timer_free(timers[i].odt);
timers[i].odt = NULL;
}
err:
return ret;
}
static int _init_gpt(void)
{
int irqno;
int ret = 0;
if ((gpt_pwm_list[IRBLASTER_PWM].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_PWM].no)) == NULL) {
printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no);
return -ENODEV;
}
omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_PWM].timer, gpt_pwm_list[IRBLASTER_PWM].source);
gpt_pwm_list[IRBLASTER_PWM].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_PWM].timer));
printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no, gpt_pwm_list[IRBLASTER_PWM].rate);
if ((gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_TIMER_CTRL].no)) == NULL) {
printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no);
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer);
return -ENODEV;
}
omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, gpt_pwm_list[IRBLASTER_TIMER_CTRL].source);
gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer));
printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no, gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate);
/* select irblaster configuration */
_select_irb_config();
/* enable timer clock */
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
/* set modulation mod */
/* trigger on overflow and match */
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2);
omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 0, 1, 2);
//if ( gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config )
// omap_cfg_reg(gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config);
irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
if (request_irq(irqno, omap2_irblaster_timer_interrupt,
IRQF_DISABLED, "gp timer", NULL)) {
ret = -EBUSY;
goto failed_request_irq;
}
omap_dm_timer_set_int_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, IRBLASTER_TIMER_CTRL_IT_TYPE);
/* disable timer clocks after init */
omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_PWM].timer);
init_waitqueue_head(&irb_wait);
_gio_debug_init();
return 0;
failed_request_irq:
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer);
omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer);
return ret;
}
/*
* Release dmtimer
* TESTED
*/
void HRTDriver_release_timer(struct omap_dm_timer *timer) {
omap_dm_timer_disable(timer);
omap_dm_timer_free(timer);
}
static int omap_pwm_led_probe(struct platform_device *pdev)
{
struct omap_pwm_led_platform_data *pdata = pdev->dev.platform_data;
struct omap_pwm_led *led;
int ret;
led = kzalloc(sizeof(struct omap_pwm_led), GFP_KERNEL);
if (led == NULL) {
dev_err(&pdev->dev, "No memory for device\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, led);
led->cdev.brightness_set = omap_pwm_led_set;
led->cdev.default_trigger = pdata->default_trigger;
led->cdev.name = pdata->name;
led->pdata = pdata;
led->brightness = LED_OFF;
INIT_WORK(&led->work, omap_pwm_led_work);
dev_info(&pdev->dev, "OMAP PWM LED (%s) at GP timer %d/%d\n",
pdata->name, pdata->intensity_timer, pdata->blink_timer);
/* register our new led device */
ret = led_classdev_register(&pdev->dev, &led->cdev);
if (ret < 0) {
dev_err(&pdev->dev, "led_classdev_register failed\n");
goto error_classdev;
}
/* get related dm timers */
led->intensity_timer = omap_dm_timer_request_specific(pdata->intensity_timer);
if (led->intensity_timer == NULL) {
dev_err(&pdev->dev, "failed to request intensity pwm timer\n");
ret = -ENODEV;
goto error_intensity;
}
omap_pwm_led_set(&led->cdev, led->brightness);
omap_dm_timer_disable(led->intensity_timer);
if (pdata->blink_timer != 0) {
led->blink_timer = omap_dm_timer_request_specific(pdata->blink_timer);
if (led->blink_timer == NULL) {
dev_err(&pdev->dev, "failed to request blinking pwm timer\n");
ret = -ENODEV;
goto error_blink1;
}
omap_dm_timer_disable(led->blink_timer);
ret = device_create_file(led->cdev.dev,
&dev_attr_on_period);
if(ret)
goto error_blink2;
ret = device_create_file(led->cdev.dev,
&dev_attr_off_period);
if(ret)
goto error_blink3;
}
return 0;
error_blink3:
device_remove_file(led->cdev.dev,
&dev_attr_on_period);
error_blink2:
dev_err(&pdev->dev, "failed to create device file(s)\n");
error_blink1:
omap_dm_timer_free(led->intensity_timer);
error_intensity:
led_classdev_unregister(&led->cdev);
error_classdev:
kfree(led);
return ret;
}
