static void omap1610_irda_rx_dma_callback(int lch, u16 ch_status, void *data)
{
struct net_device *dev = data;
struct omap1610_irda *si = dev->priv;
printk(KERN_ERR "RX Transfer error or very big frame \n");
/* Clear interrupts */
omap_readb(UART3_IIR);
si->stats.rx_frame_errors++;
omap_readb(UART3_RESUME);
/* Re-init RX DMA */
omap1610_irda_start_rx_dma(si);
}
static void ohci_context_save(void)
{
int i;
if (is_sil_rev_less_than(OMAP3430_REV_ES3_1)) {
ohci_context.usbtll_sysconfig =
omap_readl(OMAP_USBTLL_SYSCONFIG);
ohci_context.usbtll_irqenable =
omap_readl(OMAP_USBTLL_IRQENABLE);
ohci_context.tll_shared_conf =
omap_readl(OMAP_TLL_SHARED_CONF);
for (i = 0; i < 3; i++) {
ohci_context.tll_channel_conf[i] =
omap_readl(OMAP_TLL_CHANNEL_CONF(i));
ohci_context.ulpi_function_ctrl[i] =
omap_readb(OMAP_TLL_ULPI_FUNCTION_CTRL(i));
ohci_context.ulpi_interface_ctrl[i] =
omap_readb(OMAP_TLL_ULPI_INTERFACE_CTRL(i));
ohci_context.ulpi_otg_ctrl[i] =
omap_readb(OMAP_TLL_ULPI_OTG_CTRL(i));
ohci_context.ulpi_usb_int_en_rise[i] =
omap_readb(OMAP_TLL_ULPI_INT_EN_RISE(i));
ohci_context.ulpi_usb_int_en_fall[i] =
omap_readb(OMAP_TLL_ULPI_INT_EN_FALL(i));
ohci_context.ulpi_usb_int_status[i] =
omap_readb(OMAP_TLL_ULPI_INT_STATUS(i));
}
}
}
void musb_enable_vbus(struct musb *musb)
{
int val;
/* enable VBUS valid, id groung*/
omap_writel(0x00000005, 0x4A00233C);
/* start the session */
val = omap_readb(0x4A0AB060);
val |= 0x1;
omap_writel(val, 0x4A0AB060);
while (musb_readb(musb->mregs, MUSB_DEVCTL)&0x80) {
mdelay(20);
DBG(1, "devcontrol before vbus=%x\n", musb_readb(musb->mregs,
MUSB_DEVCTL));
}
if (musb->xceiv->set_vbus)
otg_set_vbus(musb->xceiv, 1);
}
static irqreturn_t
omap1610_irda_irq(int irq, void *dev_id, struct pt_regs *hw_regs)
{
struct net_device *dev = dev_id;
struct omap1610_irda *si = dev->priv;
struct sk_buff *skb;
u8 status;
int w = 0;
__ECHO_IN;
/* Clear EOF interrupt */
status = omap_readb(UART3_IIR);
if (status & (1 << 5)) {
u8 mdr2 = omap_readb(UART3_MDR2);
HDBG1(2);
if (mdr2 & 1)
printk(KERN_ERR "IRDA Buffer underrun error");
si->stats.tx_packets++;
if (si->newspeed) {
omap1610_irda_set_speed(dev, si->newspeed);
si->newspeed = 0;
}
netif_wake_queue(dev);
if (!(status & 0x80))
return IRQ_HANDLED;
}
/* Stop DMA and if there are no errors, send frame to upper layer */
omap_stop_dma(si->rx_dma_channel);
status = omap_readb(UART3_SFLSR); /* Take a frame status */
if (status != 0) { /* Bad frame? */
si->stats.rx_frame_errors++;
omap_readb(UART3_RESUME);
} else {
/* We got a frame! */
skb = alloc_skb(4096, GFP_ATOMIC);
if (!skb) {
printk(KERN_ERR "omap_sir: out of memory for RX SKB\n");
return IRQ_HANDLED;
}
/*
* Align any IP headers that may be contained
* within the frame.
*/
skb_reserve(skb, 1);
w = omap_readw(OMAP_DMA_CDAC(si->rx_dma_channel));
w -= omap_readw(OMAP_DMA_CDSA_L(si->rx_dma_channel));
if (si->speed != 4000000) {
memcpy(skb_put(skb, w - 2), si->rx_buf_dma_virt, w - 2); /* Copy DMA buffer to skb */
} else {
memcpy(skb_put(skb, w - 4), si->rx_buf_dma_virt, w - 4); /* Copy DMA buffer to skb */
}
skb->dev = dev;
skb->mac.raw = skb->data;
skb->protocol = htons(ETH_P_IRDA);
si->stats.rx_packets++;
si->stats.rx_bytes += skb->len;
netif_receive_skb(skb); /* Send data to upper level */
}
/* Re-init RX DMA */
omap1610_irda_start_rx_dma(si);
dev->last_rx = jiffies;
__ECHO_OUT;
return IRQ_HANDLED;
}
static int omap1610_irda_startup(struct net_device *dev)
{
__ECHO_IN;
/* Enable UART3 clock and set UART3 to IrDA mode */
omap_writel(omap_readl(MOD_CONF_CTRL_0) | (1 << 31) | (1 << 15),
MOD_CONF_CTRL_0);
if (machine_is_omap_h2()) {
// omap_cfg_reg(Y15_1610_GPIO17);
omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
omap_set_gpio_direction(OMAP1610_H2_FIRSEL_GPIO, 0);
omap_set_gpio_dataout(OMAP1610_H2_FIRSEL_GPIO, 0);
}
omap_writeb(0x07, UART3_MDR1); /* Put UART3 in reset mode */
/* Clear DLH and DLL */
omap_writeb(1 << 7, UART3_LCR);
omap_writeb(0, UART3_DLL);
omap_writeb(0, UART3_DLH);
omap_writeb(0xbf, UART3_LCR);
omap_writeb(1 << 4, UART3_EFR);
omap_writeb(1 << 7, UART3_LCR);
/* Enable access to UART3_TLR and UART3_TCR registers */
omap_writeb(1 << 6, UART3_MCR);
omap_writeb(0, UART3_SCR);
/* Set Rx trigger to 1 and Tx trigger to 1 */
omap_writeb(0, UART3_TLR);
/* Set LCR to 8 bits and 1 stop bit */
omap_writeb(0x03, UART3_LCR);
/* Clear RX and TX FIFO and enable FIFO */
/* Use DMA Req for transfers */
omap_writeb((1 << 2) | (1 << 1) | (1 << 3) | (1 << 4) | (1 << 6) | 1,
UART3_FCR);
omap_writeb(0, UART3_MCR);
omap_writeb((1 << 7) | (1 << 6), UART3_SCR);
/* Enable UART3 SIR Mode,(Frame-length method to end frames) */
omap_writeb(1, UART3_MDR1);
/* Set Status FIFO trig to 1 */
omap_writeb(0, UART3_MDR2);
/* Enables RXIR input */
/* and disable TX underrun */
/* SEND_SIP pulse */
// omap_writeb((1 << 7) | (1 << 6) | (1 << 4), UART3_ACREG);
omap_writeb((1 << 6) | (1 << 4), UART3_ACREG);
/* Enable EOF Interrupt only */
omap_writeb((1 << 7) | (1 << 5), UART3_IER);
/* Set Maximum Received Frame size to 2048 bytes */
omap_writeb(0x00, UART3_RXFLL);
omap_writeb(0x08, UART3_RXFLH);
omap_readb(UART3_RESUME);
__ECHO_OUT;
return 0;
}
/*
* Sets the Omap MUX and PULL_DWN registers based on the table
*/
int __init_or_module omap_cfg_reg(const unsigned long index)
{
static DEFINE_RAW_SPINLOCK(mux_spin_lock);
unsigned long flags;
struct pin_config *cfg;
unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
pull_orig = 0, pull = 0;
unsigned int mask, warn = 0;
if (!pin_table)
BUG();
if (index >= pin_table_sz) {
printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
index, pin_table_sz);
dump_stack();
return -ENODEV;
}
cfg = (struct pin_config *)&pin_table[index];
if (cpu_is_omap24xx()) {
u8 reg = 0;
reg |= cfg->mask & 0x7;
if (cfg->pull_val)
reg |= OMAP24XX_PULL_ENA;
if(cfg->pu_pd_val)
reg |= OMAP24XX_PULL_UP;
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
{
u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
u8 debug = 0;
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
#endif
warn = (orig != reg);
if (debug || warn)
printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
cfg->name,
OMAP24XX_L4_BASE + cfg->mux_reg,
orig, reg);
}
#endif
omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
return 0;
}
/* Check the mux register in question */
if (cfg->mux_reg) {
unsigned tmp1, tmp2;
spin_lock_irqsave(&mux_spin_lock, flags);
reg_orig = omap_readl(cfg->mux_reg);
/* The mux registers always seem to be 3 bits long */
mask = (0x7 << cfg->mask_offset);
tmp1 = reg_orig & mask;
reg = reg_orig & ~mask;
tmp2 = (cfg->mask << cfg->mask_offset);
reg |= tmp2;
if (tmp1 != tmp2)
warn = 1;
omap_writel(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
/* Check for pull up or pull down selection on 1610 */
if (!cpu_is_omap1510()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
spin_lock_irqsave(&mux_spin_lock, flags);
pu_pd_orig = omap_readl(cfg->pu_pd_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pu_pd_val) {
if (!(pu_pd_orig & mask))
warn = 1;
/* Use pull up */
pu_pd = pu_pd_orig | mask;
} else {
if (pu_pd_orig & mask)
warn = 1;
/* Use pull down */
pu_pd = pu_pd_orig & ~mask;
}
omap_writel(pu_pd, cfg->pu_pd_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
}
/* Check for an associated pull down register */
if (cfg->pull_reg) {
spin_lock_irqsave(&mux_spin_lock, flags);
pull_orig = omap_readl(cfg->pull_reg);
mask = 1 << cfg->pull_bit;
if (cfg->pull_val) {
if (pull_orig & mask)
warn = 1;
/* Low bit = pull enabled */
pull = pull_orig & ~mask;
} else {
if (!(pull_orig & mask))
warn = 1;
/* High bit = pull disabled */
pull = pull_orig | mask;
}
omap_writel(pull, cfg->pull_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
}
if (warn) {
#ifdef CONFIG_OMAP_MUX_WARNINGS
printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
#endif
}
#ifdef CONFIG_OMAP_MUX_DEBUG
if (cfg->debug || warn) {
printk("MUX: Setting register %s\n", cfg->name);
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
if (!cpu_is_omap1510()) {
if (cfg->pu_pd_reg && cfg->pull_val) {
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pu_pd_name, cfg->pu_pd_reg,
pu_pd_orig, pu_pd);
}
}
if (cfg->pull_reg)
printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
cfg->pull_name, cfg->pull_reg, pull_orig, pull);
}
#endif
#ifdef CONFIG_OMAP_MUX_ERRORS
return warn ? -ETXTBSY : 0;
#else
return 0;
#endif
}
static u8 inline uart_reg_in(int idx)
{
u8 b = omap_readb(idx);
return b;
}
static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
{
int i;
/* Use UTMI Ports of TLL */
omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN_SHIFT)|
(1<<OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN_SHIFT)|
(0<<OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN_SHIFT),
OMAP_UHH_HOSTCONFIG);
/* Enusre bit is set */
while (!(omap_readl(OMAP_UHH_HOSTCONFIG)
& (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)))
cpu_relax();
dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
/* Program the 3 TLL channels upfront */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
/* Disable AutoIdle */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
/* Disable BitStuffing */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
/* SDR Mode */
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
}
/* Program Common TLL register */
omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
(1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
(0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
(0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
OMAP_TLL_SHARED_CONF);
/* Enable channels now */
for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
/* Enable only the channel that is needed */
if (!(tll_channel_mask & 1<<i))
continue;
omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
(1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
OMAP_TLL_CHANNEL_CONF(i));
omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
"= 0x%02x\n",
i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
}
}
