static int __init smsc_setup(void) { unsigned char devid, devrev; smsc_virt = onchip_remap(SMSC_BASE, 1024, "SMSC"); if (!smsc_virt) { panic("Unable to remap SMSC\n"); } /* Initially the chip is in run state */ /* Put it into configuration state */ outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); /* Read device ID info */ devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX); devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX); printk("SMSC devid %02x rev %02x\n", devid, devrev); /* Select the keyboard device */ SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); /* enable it */ SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); /* Select the interrupts */ /* On a PC keyboard is IRQ1, mouse is IRQ12 */ SMSC_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX); SMSC_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX); /* Exit the configuraton state */ outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); return 0; }
void __init arch_init_clk_ops(struct clk_ops **ops, int idx) { cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); BUG_ON(!cprc_base); if (idx < ARRAY_SIZE(sh5_clk_ops)) *ops = sh5_clk_ops[idx]; }
void init_cayman_irq(void) { int i; epld_virt = onchip_remap(EPLD_BASE, 1024, "EPLD"); if (!epld_virt) { printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n"); return; } for (i=0; i<NR_EXT_IRQS; i++) { irq_desc[START_EXT_IRQS + i].chip = &cayman_irq_type; } /* Setup the SMSC interrupt */ setup_irq(SMSC_IRQ, &cayman_action_smsc); setup_irq(PCI2_IRQ, &cayman_action_pci2); }
int __init sh5pci_init(unsigned long memStart, unsigned long memSize) { u32 lsr0; u32 uval; if (request_irq(IRQ_ERR, pcish5_err_irq, IRQF_DISABLED, "PCI Error",NULL) < 0) { printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n"); return -EINVAL; } if (request_irq(IRQ_SERR, pcish5_serr_irq, IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) { printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n"); return -EINVAL; } pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR"); if (!pcicr_virt) { panic("Unable to remap PCICR\n"); } PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); if (!PCI_IO_AREA) { panic("Unable to remap PCIIO\n"); } /* Clear snoop registers */ SH5PCI_WRITE(CSCR0, 0); SH5PCI_WRITE(CSCR1, 0); /* Switch off interrupts */ SH5PCI_WRITE(INTM, 0); SH5PCI_WRITE(AINTM, 0); SH5PCI_WRITE(PINTM, 0); /* Set bus active, take it out of reset */ uval = SH5PCI_READ(CR); /* Set command Register */ SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | CR_PFCS | CR_BMAM); uval=SH5PCI_READ(CR); /* Allow it to be a master */ /* NB - WE DISABLE I/O ACCESS to stop overlap */ /* set WAIT bit to enable stepping, an attempt to improve stability */ SH5PCI_WRITE_SHORT(CSR_CMD, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_WAIT); /* ** Set translation mapping memory in order to convert the address ** used for the main bus, to the PCI internal address. */ SH5PCI_WRITE(MBR,0x40000000); /* Always set the max size 512M */ SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024)); /* ** I/O addresses are mapped at internal PCI specific address ** as is described into the configuration bridge table. ** These are changed to 0, to allow cards that have legacy ** io such as vga to function correctly. We set the SH5 IOBAR to ** 256K, which is a bit big as we can only have 64K of address space */ SH5PCI_WRITE(IOBR,0x0); /* Set up a 256K window. Totally pointless waste of address space */ SH5PCI_WRITE(IOBMR,0); /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. * Ideally, we would want to map the I/O region somewhere, but it * is so big this is not that easy! */ SH5PCI_WRITE(CSR_IBAR0,~0); /* Set memory size value */ memSize = memory_end - memory_start; /* Now we set up the mbars so the PCI bus can see the memory of * the machine */ if (memSize < (1024 * 1024)) { printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n", memSize); return -EINVAL; } /* Set LSR 0 */ lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : ((r2p2(memSize) - 0x100000) | 0x1); SH5PCI_WRITE(LSR0, lsr0); /* Set MBAR 0 */ SH5PCI_WRITE(CSR_MBAR0, memory_start); SH5PCI_WRITE(LAR0, memory_start); SH5PCI_WRITE(CSR_MBAR1,0); SH5PCI_WRITE(LAR1,0); SH5PCI_WRITE(LSR1,0); /* Enable the PCI interrupts on the device */ SH5PCI_WRITE(INTM, ~0); SH5PCI_WRITE(AINTM, ~0); SH5PCI_WRITE(PINTM, ~0); return 0; }
static int __init smsc_superio_setup(void) { unsigned char devid, devrev; smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO"); if (!smsc_superio_virt) { panic("Unable to remap SMSC SuperIO\n"); } /* Initially the chip is in run state */ /* Put it into configuration state */ outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); /* Read device ID info */ devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX); devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX); printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev); /* Select the keyboard device */ SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX); /* enable it */ SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); /* Select the interrupts */ /* On a PC keyboard is IRQ1, mouse is IRQ12 */ SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX); SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX); #ifdef CONFIG_IDE /* * Only IDE1 exists on the Cayman */ /* Power it on */ SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22); SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX); SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX); SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8, SMSC_PRIMARY_BASE_INDEX + 0); SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff, SMSC_PRIMARY_BASE_INDEX + 1); SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8, SMSC_SECONDARY_BASE_INDEX + 0); SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff, SMSC_SECONDARY_BASE_INDEX + 1); SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX); SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX); SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */ SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */ SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */ SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */ #endif /* Exit the configuration state */ outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR); return 0; }