void main(void)
{
EA = 1;
init_timer();
init_master(MASTER_HOST_ID, COMM_SPEED_9600_H);
operate_master();
}
static cycles_t
operate(conf_object_t *self,
conf_object_t *mem_space,
map_list_t *map_list,
generic_transaction_t *mem_op)
{
uart_sampler_t *s = (uart_sampler_t *)self;
uart_sampler_conf_t *c = (uart_sampler_conf_t *)s->conf;
usf_access_t ref;
if (!s->active)
return 0;
if (SIM_mem_op_is_prefetch(mem_op)) {
SIM_log_info(4, &s->log, 0, "Ignoring prefetch");
return 0;
}
if (SIM_mem_op_is_control(mem_op)) {
SIM_log_info(4, &s->log, 0, "Ignoring control");
return 0;
}
assert(SIM_mem_op_is_data(mem_op));
assert(SIM_mem_op_is_from_cpu(mem_op));
ref.pc = eip((mem_op)->ini_ptr);
ref.addr = mem_op->physical_address;
ref.time = s->time;
ref.tid = cpuid((mem_op)->ini_ptr);
ref.len = mem_op->size;
ref.type = SIM_mem_op_is_read(mem_op) ? USF_ATYPE_RD : USF_ATYPE_WR;
if (c->master)
operate_master(s, c, &ref);
else
operate_slave(s, c, &ref);
s->time++;
return 0;
}
