int main() {
// Wakeup timer value
//mbus_write_message32(0xAA,*REG_WUPT_VAL);
// Only enable relevant interrupts (PRCv17)
//enable_reg_irq();
//enable_all_irq();
*NVIC_ISER = (1 << IRQ_WAKEUP) | (1 << IRQ_GOCEP) | (1 << IRQ_TIMER32) | (1 << IRQ_REG0)| (1 << IRQ_REG1)| (1 << IRQ_REG2)| (1 << IRQ_REG3);
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
config_timerwd(TIMERWD_VAL);
// Initialization sequence
if (enumerated != 0xDEADBEE0){
operation_init();
sns_wakeup_timer_test();
}
set_halt_until_mbus_tx();
mbus_write_message32(0xAA,0xABCD1234);
delay(MBUS_DELAY);
//sns_temp_test();
//set_wakeup_timer(WAKEUP_PERIOD_CONT, 0x1, 0x1);
//mbus_write_message32(0xFF,*REG_WUPT_VAL);
operation_sleep();
while(1);
}
/*
* pfree -- deallocates a memory block previously allocated by pmalloc
*
* A zero value is written persistently into the off variable.
*
* If successful function returns zero. Otherwise an error number is returned.
*/
void
pfree(PMEMobjpool *pop, uint64_t *off)
{
struct redo_log *redo = pmalloc_redo_hold(pop);
struct operation_context ctx;
operation_init(&ctx, pop, pop->redo, redo);
int ret = pmalloc_operation(&pop->heap, *off, off, 0, NULL, NULL, &ctx);
ASSERTeq(ret, 0);
pmalloc_redo_release(pop);
}
/*
* prealloc -- resizes in-place a previously allocated memory block
*
* The block offset is written persistently into the off variable.
*
* If successful function returns zero. Otherwise an error number is returned.
*/
int
prealloc(PMEMobjpool *pop, uint64_t *off, size_t size)
{
struct redo_log *redo = pmalloc_redo_hold(pop);
struct operation_context ctx;
operation_init(&ctx, pop, pop->redo, redo);
int ret = pmalloc_operation(&pop->heap, *off, off, size, NULL, 0, &ctx);
pmalloc_redo_release(pop);
return ret;
}
//***************************************************************************************
// MAIN function starts here
//***************************************************************************************
int main() {
mbus_write_message32(0xAA, 0x11111111);
// Reset Wakeup Timer; This is required for PRCv13
set_wakeup_timer(100, 0, 1);
// Initialize Interrupts
// Only enable register-related interrupts
enable_reg_irq();
mbus_write_message32(0xAA, 0x22222222);
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
config_timerwd(40000000); // 2e7: 1min
//config_timerwd(0xFFFFF); // 0xFFFFF about 13 sec with Y2 run default clock
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
// Check if wakeup is due to GOC interrupt
// 0x78 is reserved for GOC-triggered wakeup (Named IRQ14VEC)
// 8 MSB bits of the wakeup data are used for function ID
uint32_t wakeup_data = *((volatile uint32_t *) IRQ14VEC);
mbus_write_message32(0xAA, 0x33333333);
mbus_write_message32(0xBB, wakeup_data);
mbus_write_message32(0xAA, 0x44444444);
if (wakeup_data){
// Memory dump
mbus_copy_mem_from_local_to_remote_stream(0,0xA,(uint32_t*)0,1023);
mbus_write_message32(0xCC, 0xABCD1234);
operation_sleep_for(2);
}else{
uint32_t count;
for(count=0; count<100; count++ ){
mbus_write_message32(0xAA, 0x44444444);
delay(MBUS_DELAY*10);
}
operation_sleep_for(2);
}
while(1);
}
/*
* pmalloc_construct -- allocates a new block of memory with a constructor
*
* The block offset is written persistently into the off variable, but only
* after the constructor function has been called.
*
* If successful function returns zero. Otherwise an error number is returned.
*/
int
pmalloc_construct(PMEMobjpool *pop, uint64_t *off, size_t size,
palloc_constr constructor, void *arg)
{
struct redo_log *redo = pmalloc_redo_hold(pop);
struct operation_context ctx;
operation_init(&ctx, pop, pop->redo, redo);
int ret = pmalloc_operation(&pop->heap, 0, off, size, constructor, arg,
&ctx);
pmalloc_redo_release(pop);
return ret;
}
//***************************************************************************************
// MAIN function starts here
//***************************************************************************************
int main() {
//Clear All Pending Interrupts
*((volatile uint32_t *) 0xE000E280) = 0xF;
//Enable Interrupts
*((volatile uint32_t *) 0xE000E100) = 0xF;
// Config watchdog timer to about 30 sec: 3,000,000 with default PRCv9
//config_timer( timer_id, go, roi, init_val, sat_val )
config_timer( 0, 1, 0, 0, 3000000 );
operation_init();
delay(MBUS_DELAY);
// Should not reach here
operation_sleep_notimer();
while(1);
}
/*
* heap_init_free_chunk -- initializes free chunk transient state
*/
static void
heap_init_free_chunk(struct palloc_heap *heap,
struct chunk_header *hdr,
struct memory_block *m)
{
struct operation_context ctx;
operation_init(&ctx, heap->base, NULL, NULL);
ctx.p_ops = &heap->p_ops;
heap_chunk_write_footer(hdr, hdr->size_idx);
/*
* Perform coalescing just in case there
* are any neighbouring free chunks.
*/
struct memory_block nm = heap_coalesce_huge(heap, m);
if (nm.chunk_id != m->chunk_id) {
m->m_ops->prep_hdr(&nm, MEMBLOCK_FREE, &ctx);
operation_process(&ctx);
}
*m = nm;
bucket_insert_block(heap->rt->default_bucket, m);
}
int main(int argc, char** argv) {
if (argc <= 1) {
return usage(argv[0], EXIT_FAILURE);
}
if (strncmp(argv[1], "-h", 3) == 0 || strncmp(argv[1], "--help", 7) == 0) {
return usage(argv[0], EXIT_SUCCESS);
}
FILE* file = fopen(argv[1], "r");
operation_t* op = operation_init(OP_INVENTORY);
while (read_operation(file, op) > 0) {
dump_operation(op);
operation_reset(op);
}
operation_delete(op);
return EXIT_SUCCESS;
}
int main() {
// Reset Wakeup Timer; This is required for PRCv13
set_wakeup_timer(100, 0, 1);
// Initialize Interrupts
// Only enable register-related interrupts
enable_reg_irq();
disable_timerwd();
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
while(1);
// Should not reach here
while(1);
}
int main() {
// Only enable relevant interrupts (PRCv17)
//enable_reg_irq();
//enable_all_irq();
*NVIC_ISER = (1 << IRQ_WAKEUP) | (1 << IRQ_GOCEP) | (1 << IRQ_TIMER32) | (1 << IRQ_REG0)| (1 << IRQ_REG1)| (1 << IRQ_REG2)| (1 << IRQ_REG3);
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
config_timerwd(TIMERWD_VAL);
// Initialization sequence
if (enumerated != 0xDEADBEE0){
operation_init();
}
while(1){
operation_sns_run();
}
operation_sleep_notimer();
while(1);
}
int main() {
// Initialize Interrupts
// Only enable register-related interrupts
//enable_reg_irq();
*NVIC_ISER = (1 << IRQ_WAKEUP) | (1 << IRQ_GOCEP) | (1 << IRQ_TIMER32) | (1 << IRQ_REG0)| (1 << IRQ_REG1)| (1 << IRQ_REG2)| (1 << IRQ_REG3);
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
//config_timerwd(0xFFFFF); // 0xFFFFF about 13 sec with Y2 run default clock
disable_timerwd();
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
// EN_OSC
sntv3_r08.TMR_SLEEP = 0x0; // Default : 0x1
sntv3_r08.TMR_ISOLATE = 0x0; // Default : 0x1
mbus_remote_register_write(SNT_ADDR,0x08,sntv3_r08.as_int);
delay(2000);
// TIMER SELF_EN Disable
sntv3_r09.TMR_SELF_EN = 0x0; // Default : 0x1
mbus_remote_register_write(SNT_ADDR,0x09,sntv3_r09.as_int);
// EN_OSC
sntv3_r08.TMR_EN_OSC = 0x1; // Default : 0x0
mbus_remote_register_write(SNT_ADDR,0x08,sntv3_r08.as_int);
// Release Reset
sntv3_r08.TMR_RESETB = 0x1; // Default : 0x0
sntv3_r08.TMR_RESETB_DIV = 0x1; // Default : 0x0
sntv3_r08.TMR_RESETB_DCDC = 0x1; // Default : 0x0
mbus_remote_register_write(SNT_ADDR,0x08,sntv3_r08.as_int);
delay(2000);
// TIMER EN_SEL_CLK Reset
sntv3_r08.TMR_EN_SELF_CLK = 0x1; // Default : 0x0
mbus_remote_register_write(SNT_ADDR,0x08,sntv3_r08.as_int);
delay(10);
// TIMER SELF_EN
sntv3_r09.TMR_SELF_EN = 0x1; // Default : 0x0
mbus_remote_register_write(SNT_ADDR,0x09,sntv3_r09.as_int);
delay(100000);
// TIMER EN_SEL_CLK Reset
sntv3_r08.TMR_EN_OSC = 0x0; // Default : 0x0
mbus_remote_register_write(SNT_ADDR,0x08,sntv3_r08.as_int);
delay(100);
// mbus_sleep_all();
// operation_sleep_notimer();
while (1){
delay(1000);
}
return 1;
}
//***************************************************************************************
// MAIN function starts here
//***************************************************************************************
int main() {
//Clear All Pending Interrupts
*((volatile uint32_t *) 0xE000E280) = 0xF;
//Enable Interrupts
*((volatile uint32_t *) 0xE000E100) = 0xF;
//Config watchdog timer to about 10 sec: 1,000,000 with default PRCv9
//config_timer( timer_id, go, roi, init_val, sat_val )
config_timer( 0, 0, 0, 0, 1000000 ); // Check with Gyouho
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
delay(10000);
read_mbus_register(MRR_ADDR, 0x0, 0xE0);
delay(MBUS_DELAY*10);
delay(10000);
read_mbus_register(MRR_ADDR, 0xE, 0xE1);
delay(MBUS_DELAY*10);
//delay(10000);
//Digital monitoring
//0-DCP_S 2-TX 3-RX C-REC_RST
mrrv2_r12.MRR_EN_DIG_MONITOR = 0x0; // Enable monitor
write_mbus_register(MRR_ADDR,0x12,mrrv2_r12.as_int);
delay(MBUS_DELAY*10);
mrrv2_r13.MRR_DIG_MONITOR_SEL1 = 0x0;
mrrv2_r13.MRR_DIG_MONITOR_SEL2 = 0x1;
mrrv2_r13.MRR_DIG_MONITOR_SEL3 = 0x2;
write_mbus_register(MRR_ADDR,0x13,mrrv2_r13.as_int);
delay(MBUS_DELAY*10);
//TX Set-up
mrrv2_r00.MRR_TRX_CAP_ANTP_TUNE = 0x3FFF; //ANT CAP 14b unary
write_mbus_register(MRR_ADDR,0x00,mrrv2_r00.as_int);
delay(MBUS_DELAY*10);
mrrv2_r01.MRR_TRX_CAP_ANTN_TUNE = 0x3FFF ; //ANT CAP 14b unary
write_mbus_register(MRR_ADDR,0x01,mrrv2_r01.as_int);
delay(MBUS_DELAY*10);
mrrv2_r02.MRR_TX_BIAS_TUNE = 0x1FFF; //Set TX BIAS TUNE 13b
write_mbus_register(MRR_ADDR,0x02,mrrv2_r02.as_int);
delay(MBUS_DELAY*10);
//RX Set-up
mrrv2_r03.MRR_RX_BIAS_TUNE = 0x0000;// 0x1FFF; // turn on Q_enhancement
mrrv2_r03.MRR_RX_SAMPLE_CAP = 0x1; // RX_SAMPLE_CAP
write_mbus_register(MRR_ADDR,3,mrrv2_r03.as_int);
delay(MBUS_DELAY*10);
/*
mrrv2_r11.MRR_RAD_FSM_RX_POWERON_LEN = 0x3; //Set RX Power on length
mrrv2_r11.MRR_RAD_FSM_RX_SAMPLE_LEN = 0x0; //Set RX Sample length
mrrv2_r11.MRR_RAD_FSM_GUARD_LEN = 0x0FFF; //Set TX_RX Guard length
write_mbus_register(MRR_ADDR,0x11,mrrv2_r11.as_int);
delay(MBUS_DELAY*10);
*/
mrrv2_r12.MRR_RAD_FSM_RX_HDR_BITS = 0x08; //Set RX header
mrrv2_r12.MRR_RAD_FSM_RX_HDR_TH = 0x00; //Set RX header threshold
mrrv2_r12.MRR_RAD_FSM_RX_DATA_BITS = 0xAA; //Set RX data
write_mbus_register(MRR_ADDR,0x12,mrrv2_r12.as_int);
delay(MBUS_DELAY*10);
//DCP set-up
mrrv2_r03.MRR_DCP_S_OW = 0;
write_mbus_register(MRR_ADDR,0x03,mrrv2_r03.as_int);
//Timer set-up
//mrrv2_r05.MRR_EN_CLK_MONITOR = 1; //
write_mbus_register(MRR_ADDR,0x05,mrrv2_r05.as_int);
delay(MBUS_DELAY*10);
//RAD_FSM set-up
mrrv2_r0E.MRR_RAD_FSM_TX_H_LEN = 31; //31-31b header (max)
mrrv2_r0E.MRR_RAD_FSM_TX_D_LEN = 24; //0-skip tx data
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*10);
//mrrv2_r0F.MRR_RAD_FSM_TX_PW_LEN = 0; //4us PW
//mrrv2_r10.MRR_RAD_FSM_TX_C_LEN = 32; // (PW_LEN+1):C_LEN=1:32
//mrrv2_r0F.MRR_RAD_FSM_TX_PS_LEN = 0; // PW=PS
//mrrv2_r0F.MRR_RAD_FSM_TX_PW_LEN = 1; //8us PW
//mrrv2_r10.MRR_RAD_FSM_TX_C_LEN = 64; // (PW_LEN+1):C_LEN=1:32
//mrrv2_r0F.MRR_RAD_FSM_TX_PS_LEN = 1; // PW=PS
//mrrv2_r0F.MRR_RAD_FSM_TX_PW_LEN = 124; //500us PW
//mrrv2_r10.MRR_RAD_FSM_TX_C_LEN = 4000; // (PW_LEN+1):C_LEN=1:32
//mrrv2_r0F.MRR_RAD_FSM_TX_PS_LEN = 124; // PW=PS
mrrv2_r0F.MRR_RAD_FSM_TX_PW_LEN = 249; //1ms PW
mrrv2_r10.MRR_RAD_FSM_TX_C_LEN = 8000; // (PW_LEN+1):C_LEN=1:32
mrrv2_r0F.MRR_RAD_FSM_TX_PS_LEN = 249; // PW=PS
mrrv2_r0F.MRR_RAD_FSM_TX_PR_LEN = 0; //
write_mbus_register(MRR_ADDR,0x0F,mrrv2_r0F.as_int);
delay(MBUS_DELAY*10);
mrrv2_r02.MRR_TX_PULSE_FINE = 0;
mrrv2_r02.MRR_TX_PULSE_FINE_TUNE = 15;
write_mbus_register(MRR_ADDR,0x02,mrrv2_r02.as_int);
delay(MBUS_DELAY*10);
mrrv2_r10.MRR_RAD_FSM_SEED = 1; //default
mrrv2_r10.MRR_RAD_FSM_TX_MODE = 3; //code rate 0:4 1:3 2:2 3:1(baseline) 4:1/2 5:1/3 6:1/4
write_mbus_register(MRR_ADDR,0x10,mrrv2_r10.as_int);
delay(MBUS_DELAY*10);
mrrv2_r11.MRR_RAD_FSM_TX_POWERON_LEN = 7; //3bits
write_mbus_register(MRR_ADDR,0x11,mrrv2_r11.as_int);
delay(MBUS_DELAY*10);
mrrv2_r06.MRR_RAD_FSM_TX_DATA_0 = 0x5555; // alternating 10
mrrv2_r07.MRR_RAD_FSM_TX_DATA_1 = 0x5555; // alternating 10
write_mbus_register(MRR_ADDR,0x06,mrrv2_r06.as_int);
delay(MBUS_DELAY*10);
//<<<<<<< HEAD
mrrv2_r07.MRR_RAD_FSM_TX_DATA_1 = 0x5555; // alternating 10
//=======
//>>>>>>> c68953f854b6cdea9e96b6411ddf33448e1c7693
write_mbus_register(MRR_ADDR,0x07,mrrv2_r07.as_int);
delay(MBUS_DELAY*10);
//CL set-up
mrrv2_r00.MRR_CL_EN = 1; //Enable CL
mrrv2_r00.MRR_CL_CTRL = 0x01; //Set CL 1-finite 16-20uA
write_mbus_register(MRR_ADDR,0x00,mrrv2_r00.as_int);
delay(MBUS_DELAY*10);
//Timer & State Machine run
mrrv2_r04.MRR_SCRO_EN_TIMER = 1; //power on TIMER
write_mbus_register(MRR_ADDR,0x04,mrrv2_r04.as_int);
delay(MBUS_DELAY*100); //LDO stab 1s
mrrv2_r04.MRR_SCRO_RSTN_TIMER = 1; //UNRST TIMER
write_mbus_register(MRR_ADDR,0x04,mrrv2_r04.as_int);
delay(MBUS_DELAY*100); //freq stab 5s
mrrv2_r04.MRR_SCRO_EN_CLK = 1; //Enable clk
write_mbus_register(MRR_ADDR,0x04,mrrv2_r04.as_int);
delay(MBUS_DELAY*100); //freq stab 5s
mrrv2_r0E.MRR_RAD_FSM_SLEEP = 0; // Power on BB
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*100);
while(1){
mrrv2_r0E.MRR_RAD_FSM_RSTN = 1; //UNRST BB
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*10);
mrrv2_r03.MRR_TRX_ISOLATEN = 1; //set ISOLATEN 1, let state machine control
write_mbus_register(MRR_ADDR,0x03,mrrv2_r03.as_int);
delay(MBUS_DELAY*10);
mrrv2_r0E.MRR_RAD_FSM_EN = 1; //Start BB
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*10);
//radio operate
//<<<<<<< HEAD
delay(MBUS_DELAY*400); //800ms pulses
//=======
// delay(MBUS_DELAY*300); //1ms pulses,1.5s packet, 1.2s idle time
//>>>>>>> c68953f854b6cdea9e96b6411ddf33448e1c7693
mrrv2_r03.MRR_TRX_ISOLATEN = 0; //set ISOLATEN 0
write_mbus_register(MRR_ADDR,0x03,mrrv2_r03.as_int);
delay(MBUS_DELAY*10);
mrrv2_r0E.MRR_RAD_FSM_EN = 0; //Stop BB
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*10);
mrrv2_r0E.MRR_RAD_FSM_RSTN = 0; //RST BB
write_mbus_register(MRR_ADDR,0x0E,mrrv2_r0E.as_int);
delay(MBUS_DELAY*10);
};
// Should not reach here
operation_sleep();
while(1);
}
static void
test_heap()
{
struct mock_pop *mpop = Malloc(MOCK_POOL_SIZE);
PMEMobjpool *pop = &mpop->p;
memset(pop, 0, MOCK_POOL_SIZE);
pop->size = MOCK_POOL_SIZE;
pop->heap_size = MOCK_POOL_SIZE - sizeof(PMEMobjpool);
pop->heap_offset = (uint64_t)((uint64_t)&mpop->heap - (uint64_t)mpop);
pop->persist = obj_heap_persist;
UT_ASSERT(heap_check(pop) != 0);
UT_ASSERT(heap_init(pop) == 0);
UT_ASSERT(heap_boot(pop) == 0);
UT_ASSERT(pop->heap != NULL);
struct bucket *b_small = heap_get_best_bucket(pop, 1);
struct bucket *b_big = heap_get_best_bucket(pop, 2048);
UT_ASSERT(b_small->unit_size < b_big->unit_size);
struct bucket *b_def = heap_get_best_bucket(pop, CHUNKSIZE);
UT_ASSERT(b_def->unit_size == CHUNKSIZE);
/* new small buckets should be empty */
UT_ASSERT(b_small->type == BUCKET_RUN);
UT_ASSERT(b_big->type == BUCKET_RUN);
struct memory_block blocks[MAX_BLOCKS] = {
{0, 0, 1, 0},
{0, 0, 1, 0},
{0, 0, 1, 0}
};
for (int i = 0; i < MAX_BLOCKS; ++i) {
heap_get_bestfit_block(pop, b_def, &blocks[i]);
UT_ASSERT(blocks[i].block_off == 0);
}
struct memory_block *blocksp[MAX_BLOCKS] = {NULL};
struct memory_block prev;
heap_get_adjacent_free_block(pop, b_def, &prev, blocks[1], 1);
UT_ASSERT(prev.chunk_id == blocks[0].chunk_id);
blocksp[0] = &prev;
struct memory_block cnt;
heap_get_adjacent_free_block(pop, b_def, &cnt, blocks[0], 0);
UT_ASSERT(cnt.chunk_id == blocks[1].chunk_id);
blocksp[1] = &cnt;
struct memory_block next;
heap_get_adjacent_free_block(pop, b_def, &next, blocks[1], 0);
UT_ASSERT(next.chunk_id == blocks[2].chunk_id);
blocksp[2] = &next;
struct operation_context *ctx = operation_init(pop, NULL);
struct memory_block result =
heap_coalesce(pop, blocksp, MAX_BLOCKS, HEAP_OP_FREE, ctx);
operation_process(ctx);
operation_delete(ctx);
UT_ASSERT(result.size_idx == 3);
UT_ASSERT(result.chunk_id == prev.chunk_id);
UT_ASSERT(heap_check(pop) == 0);
heap_cleanup(pop);
UT_ASSERT(pop->heap == NULL);
Free(mpop);
}
int main() {
// Reset Wakeup Timer; This is required for PRCv13
//set_wakeup_timer(200, 0, 1);
// Initialize Interrupts
// Only enable register-related interrupts
enable_reg_irq();
// Config watchdog timer to about 10 sec; default: 0x02FFFFFF
config_timerwd(TIMERWD_VAL);
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
// Check if wakeup is due to GOC interrupt
// 0x78 is reserved for GOC-triggered wakeup (Named IRQ14VEC)
// 8 MSB bits of the wakeup data are used for function ID
wakeup_data = *((volatile uint32_t *) IRQ14VEC);
uint8_t wakeup_data_header = wakeup_data>>24;
uint8_t wakeup_data_field_0 = wakeup_data & 0xFF;
uint8_t wakeup_data_field_1 = wakeup_data>>8 & 0xFF;
uint8_t wakeup_data_field_2 = wakeup_data>>16 & 0xFF;
// In case GOC triggered in the middle of routines
if ((wakeup_data_header != 0) && (exec_count_irq == 0)){
operation_goc_trigger_init();
}
if(wakeup_data_header == 1){
// Debug mode: Transmit something via radio and go to sleep w/o timer
// wakeup_data[7:0] is the # of transmissions
// wakeup_data[15:8] is the user-specified period
// wakeup_data[23:16] is the MSB of # of transmissions
WAKEUP_PERIOD_CONT_INIT = wakeup_data_field_1;
if (exec_count_irq < (wakeup_data_field_0 + (wakeup_data_field_2<<8))){
exec_count_irq++;
if (exec_count_irq == 1){
// Prepare radio TX
radio_power_on();
// Go to sleep for SCRO stabilitzation
set_wakeup_timer(WAKEUP_PERIOD_RADIO_INIT, 0x1, 0x1);
operation_sleep_noirqreset();
}else{
// radio
send_radio_data_ppm(0,0xABC000+exec_count_irq);
// set timer
set_wakeup_timer(WAKEUP_PERIOD_CONT_INIT, 0x1, 0x1);
// go to sleep and wake up with same condition
operation_sleep_noirqreset();
}
}else{
exec_count_irq = 0;
// radio
send_radio_data_ppm(1,0xFAF000);
// Go to sleep without timer
operation_sleep_notimer();
}
}else if(wakeup_data_header == 2){
// Slow down PMU sleep osc and run temp sensor code with desired wakeup period
// wakeup_data[15:0] is the user-specified period
// wakeup_data[19:16] is the initial user-specified period
// wakeup_data[20] enables radio tx for each measurement
// wakeup_data[23:21] specifies how many temp sensor executes; 0: unlimited, n: 50*2^n
WAKEUP_PERIOD_CONT_USER = (wakeup_data_field_0 + (wakeup_data_field_1<<8));
WAKEUP_PERIOD_CONT_INIT = (wakeup_data_field_2 & 0xF);
radio_tx_option = wakeup_data_field_2 & 0x10;
temp_run_single = 0;
//set_pmu_sleep_clk_low();
if (!temp_running){
// Go to sleep for initial settling of temp sensing // FIXME
set_wakeup_timer(WAKEUP_PERIOD_CONT_INIT, 0x1, 0x1);
temp_running = 1;
set_temp_exec_count = wakeup_data_field_2 >> 5;
exec_count_irq++;
operation_sleep_noirqreset();
}
int main() {
set_wakeup_timer(100, 0, 1); // Reset Wakeup Timer;
enable_reg_irq(); // Initialize Interrupts, Only enable register-related interrupts
config_timerwd(0x3FFFFF); // Config watchdog timer to about 10 sec (default: 0x02FFFFFF), 0xFFFFF about 13 sec with Y2 run default clock
if (enumerated != 0xDEADBEEF){
operation_init(); // Initialization
}
// Check if wakeup is due to GOC interrupt
// 0x78 is reserved for GOC-triggered wakeup (Named IRQ14VEC)
// 8 MSB bits of the wakeup data are used for function ID
wakeup_data = *((volatile uint32_t *) IRQ14VEC);
uint8_t wakeup_data_header = wakeup_data>>24;
uint8_t wakeup_data_field_0 = wakeup_data & 0xFF;
uint8_t wakeup_data_field_1 = wakeup_data>>8 & 0xFF;
uint8_t wakeup_data_field_2 = wakeup_data>>16 & 0xFF;
// In case GOC triggered in the middle of routines
if ((wakeup_data_header != 0) && (exec_count_irq == 0)){
operation_goc_trigger_init();
}
if(wakeup_data_header == 1){
// Debug mode: Transmit something via radio and go to sleep w/o timer and Change WAKEUP_PERIOD_CONT_INIT
// wakeup_data[7:0] is the LSB of # of transmissions
// wakeup_data[15:8] is the user-specified period
// wakeup_data[23:16] is the MSB of # of transmissions
WAKEUP_PERIOD_CONT_INIT = wakeup_data_field_1;
if (exec_count_irq < (wakeup_data_field_0 + (wakeup_data_field_2<<8))){
exec_count_irq++;
if (exec_count_irq == 1){
// Prepare radio TX
radio_power_on();
// Go to sleep for SCRO stabilitzation
set_wakeup_timer(WAKEUP_PERIOD_RADIO_INIT, 0x1, 0x1);
operation_sleep_noirqreset();
}else{
// radio
send_radio_data_ppm(0,0xABC000+exec_count_irq);
delay(RADIO_PACKET_DELAY); //Set delays between sending subsequent packet
// set timer
set_wakeup_timer(WAKEUP_PERIOD_CONT_INIT, 0x1, 0x1);
// go to sleep and wake up with same condition
operation_sleep_noirqreset();
}
}else{
exec_count_irq = 0;
// radio
send_radio_data_ppm(1,0xFAF000);
// Go to sleep without timer
operation_sleep_notimer();
}
}else if(wakeup_data_header == 2){
// Slow down PMU sleep osc and run sensors with desired wakeup period
// wakeup_data[15:0] is the user-specified period
// wakeup_data[19:16] is the initial user-specified period
// wakeup_data[20] enables radio tx for each measurement
// wakeup_data[23:21] specifies how many temp sensor executes; 0: unlimited, n: 50*2^n
WAKEUP_PERIOD_CONT = wakeup_data_field_0 + (wakeup_data_field_1<<8);
WAKEUP_PERIOD_CONT_INIT = wakeup_data_field_2 & 0xF;
radio_tx_option = wakeup_data_field_2 & 0x10;
//set_pmu_sleep_clk_low();
if (!sensor_running){
// Go to sleep for initial settling of sensing // FIXME
set_wakeup_timer(5, 0x1, 0x1); // 150: around 5 min
sensor_running = 1;
set_max_exec_count = wakeup_data_field_2 >> 5;
exec_count_irq++;
operation_sleep_noirqreset();
}
//***************************************************************************************
// MAIN function starts here
//***************************************************************************************
int main() {
//Clear All Pending Interrupts
*((volatile uint32_t *) 0xE000E280) = 0xF;
//Enable Interrupts
*((volatile uint32_t *) 0xE000E100) = 0xF;
//Config watchdog timer to about 10 sec: 1,000,000 with default PRCv9
//config_timer( timer_id, go, roi, init_val, sat_val )
config_timer( 0, 1, 0, 0, 1000000 );
// Initialization sequence
if (enumerated != 0xDEADBEEF){
// Set up PMU/GOC register in PRC layer (every time)
// Enumeration & RAD/SNS layer register configuration
operation_init();
}
// Check if wakeup is due to GOC interrupt
// 0x68 is reserved for GOC-triggered wakeup (Named IRQ10VEC)
// 8 MSB bits of the wakeup data are used for function ID
uint32_t wakeup_data = *((volatile uint32_t *) IRQ10VEC);
uint8_t wakeup_data_header = wakeup_data>>24;
uint8_t wakeup_data_field_0 = wakeup_data & 0xFF;
uint8_t wakeup_data_field_1 = wakeup_data>>8 & 0xFF;
uint8_t wakeup_data_field_2 = wakeup_data>>16 & 0xFF;
if(wakeup_data_header == 1){
// Debug mode: Transmit something via radio and go to sleep w/o timer
// wakeup_data[7:0] is the # of transmissions
// wakeup_data[15:8] is the user-specified period
// wakeup_data[23:16] is the MSB of # of transmissions
WAKEUP_PERIOD_CONT_INIT = wakeup_data_field_1;
delay(MBUS_DELAY);
if (exec_count_irq < (wakeup_data_field_0 + (wakeup_data_field_2<<8))){
exec_count_irq++;
if (exec_count_irq == 1){
// Prepare radio TX
radio_power_on();
// Go to sleep for SCRO stabilitzation
set_wakeup_timer(WAKEUP_PERIOD_RADIO_INIT, 0x1, 0x0);
operation_sleep_noirqreset();
}else{
// radio
send_radio_data_ppm(0,0xFAF000+exec_count_irq);
// set timer
set_wakeup_timer (WAKEUP_PERIOD_CONT_INIT, 0x1, 0x0);
// go to sleep and wake up with same condition
operation_sleep_noirqreset();
}
}else{
exec_count_irq = 0;
// radio
send_radio_data_ppm(1,0xFAF000);
// Go to sleep without timer
operation_sleep_notimer();
}
}else if(wakeup_data_header == 2){
// Slow down PMU sleep osc and run CDC code with desired wakeup period
// wakeup_data[15:0] is the user-specified period
// wakeup_data[19:16] is the initial user-specified period
// wakeup_data[20] enables radio tx for each measurement
// wakeup_data[23:21] specifies how many cdc executes; 0: unlimited, n: 50*2^n
WAKEUP_PERIOD_CONT = wakeup_data_field_0 + (wakeup_data_field_1<<8);
WAKEUP_PERIOD_CONT_INIT = wakeup_data_field_2 & 0xF;
radio_tx_option = wakeup_data_field_2 & 0x10;
set_cdc_exec_count = wakeup_data_field_2 >> 5;
cdc_run_single = 0;
//set_pmu_sleep_clk_low();
delay(MBUS_DELAY);
if (!cdc_running){
// Go to sleep for initial settling of pressure // FIXME
set_wakeup_timer (5, 0x1, 0x0); // 150: around 5 min
cdc_running = 1;
operation_sleep_noirqreset();
}
exec_count = 0;
meas_count = 0;
cdc_storage_count = 0;
radio_tx_count = 0;
// Reset IRQ10VEC
*((volatile uint32_t *) IRQ10VEC) = 0;
// Run CDC Program
cdc_reset_timeout_count = 0;
operation_cdc_run();
}else if(wakeup_data_header == 3){
/*
* heap_reclaim_run -- checks the run for available memory if unclaimed.
*
* Returns 1 if reclaimed chunk, 0 otherwise.
*/
static int
heap_reclaim_run(struct palloc_heap *heap, struct chunk_run *run,
struct memory_block *m)
{
if (m->m_ops->claim(m) != 0)
return 0; /* this run already has an owner */
struct alloc_class *c = alloc_class_get_create_by_unit_size(
heap->rt->alloc_classes, run->block_size);
if (c == NULL)
return 0;
ASSERTeq(c->type, CLASS_RUN);
pthread_mutex_t *lock = m->m_ops->get_lock(m);
util_mutex_lock(lock);
unsigned i;
unsigned nval = c->run.bitmap_nval;
for (i = 0; nval > 0 && i < nval - 1; ++i)
if (run->bitmap[i] != 0)
break;
int empty = (i == (nval - 1)) &&
(run->bitmap[i] == c->run.bitmap_lastval);
if (empty) {
struct zone *z = ZID_TO_ZONE(heap->layout, m->zone_id);
struct chunk_header *hdr = &z->chunk_headers[m->chunk_id];
struct bucket *defb = heap_get_default_bucket(heap);
/*
* The redo log ptr can be NULL if we are sure that there's only
* one persistent value modification in the entire operation
* context.
*/
struct operation_context ctx;
operation_init(&ctx, heap->base, NULL, NULL);
ctx.p_ops = &heap->p_ops;
struct memory_block nb = MEMORY_BLOCK_NONE;
nb.chunk_id = m->chunk_id;
nb.zone_id = m->zone_id;
nb.block_off = 0;
nb.size_idx = m->size_idx;
heap_chunk_init(heap, hdr, CHUNK_TYPE_FREE, nb.size_idx);
memblock_rebuild_state(heap, &nb);
nb = heap_coalesce_huge(heap, &nb);
nb.m_ops->prep_hdr(&nb, MEMBLOCK_FREE, &ctx);
operation_process(&ctx);
bucket_insert_block(defb, &nb);
*m = nb;
} else {
recycler_put(heap->rt->recyclers[c->id], m);
}
util_mutex_unlock(lock);
return empty;
}
