/*
* Configure a number of windows.
*/
static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg,
const struct orion_addr_map_info *info)
{
while (info->win != -1) {
orion_setup_cpu_win(cfg, info->win, info->base, info->size,
info->target, info->attr, info->remap);
info++;
}
}
static void __init qnap_ts209_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion_init();
/*
* Setup flash mapping
*/
orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
QNAP_TS209_NOR_BOOT_SIZE, -1);
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
* Setup Multiplexing Pins --
* MPP[0] Reserved
* MPP[1] USB copy button (0 active)
* MPP[2] Load defaults button (0 active)
* MPP[3] GPIO RTC
* MPP[4-5] Reserved
* MPP[6] PCI Int A
* MPP[7] PCI Int B
* MPP[8-11] Reserved
* MPP[12] SATA 0 presence
* MPP[13] SATA 1 presence
* MPP[14] SATA 0 active
* MPP[15] SATA 1 active
* MPP[16] UART1 RXD
* MPP[17] UART1 TXD
* MPP[18] SW_RST (0 active)
* MPP[19] Reserved
* MPP[20] PCI clock 0
* MPP[21] PCI clock 1
* MPP[22] USB 0 over current
* MPP[23-25] Reserved
*/
orion_write(MPP_0_7_CTRL, 0x3);
orion_write(MPP_8_15_CTRL, 0x55550000);
orion_write(MPP_16_19_CTRL, 0x5500);
orion_gpio_set_valid_pins(0x3cc0fff);
/* register ts209 specific power-off method */
pm_power_off = qnap_ts209_power_off;
platform_add_devices(qnap_ts209_devices,
ARRAY_SIZE(qnap_ts209_devices));
/* Get RTC IRQ and register the chip */
if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
if (gpio_direction_input(TS209_RTC_GPIO) == 0)
qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO);
else
gpio_free(TS209_RTC_GPIO);
}
if (qnap_ts209_i2c_rtc.irq == 0)
pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
orion_eth_init(&qnap_ts209_eth_data);
orion_sata_init(&qnap_ts209_sata_data);
}
void __init orion5x_setup_sram_win(void)
{
orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
TARGET_SRAM, ATTR_SRAM, -1);
}
void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
{
orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
TARGET_PCIE, ATTR_PCIE_WA, -1);
}
void __init orion5x_setup_dev2_win(u32 base, u32 size)
{
orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
}
void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
int maj, int min)
{
orion_setup_cpu_win(&addr_map_cfg, window, base, size,
TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
}
