static void otg_core_reset(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg;
osalSysPolledDelayX(32);
/* Core reset and delay of at least 3 PHY cycles.*/
otgp->GRSTCTL = GRSTCTL_CSRST;
while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0)
;
osalSysPolledDelayX(18);
/* Wait AHB idle condition.*/
while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0)
;
}
static void otg_txfifo_flush(USBDriver *usbp, uint32_t fifo) {
stm32_otg_t *otgp = usbp->otg;
otgp->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
while ((otgp->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
;
/* Wait for 3 PHY Clocks.*/
osalSysPolledDelayX(18);
}
/**
* @brief Enables the ADC voltage regulator.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_vreg_on(ADCDriver *adcp) {
adcp->adcm->CR = 0; /* RM 12.4.3.*/
adcp->adcm->CR = ADC_CR_ADVREGEN_0;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN_0;
#endif
osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
}
static void otg_rxfifo_flush(USBDriver *usbp) {
stm32_otg_t *otgp = usbp->otg;
otgp->GRSTCTL = GRSTCTL_RXFFLSH;
while ((otgp->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
;
/* Wait for 3 PHY Clocks.*/
osalSysPolledDelayX(12);
}
/**
* @brief Enables the ADC voltage regulator.
*
* @param[in] adcp pointer to the @p ADCDriver object
*/
static void adc_lld_vreg_on(ADCDriver *adcp) {
#if defined(STM32F3XX)
adcp->adcm->CR = 0; /* RM 12.4.3.*/
adcp->adcm->CR = ADC_CR_ADVREGEN_0;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN_0;
#endif
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
#endif
#if defined(STM32L4XX) || defined(STM32L4XXP)
adcp->adcm->CR = 0; /* RM 16.3.6.*/
adcp->adcm->CR = ADC_CR_ADVREGEN;
#if STM32_ADC_DUAL_MODE
adcp->adcs->CR = ADC_CR_ADVREGEN;
#endif
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));
#endif
}
void McuDelayMillisecond(const u32_t n_ms)
{
osalSysPolledDelayX(MS2RTC(STM32_HCLK, n_ms));
}