static void omap4430_phy_init_for_eyediagram(u32 swcap_trim_offset)
{
u32 read_val = 0;
u32 swcap_trim = 0;
transceiver = otg_get_transceiver();
/* If clock is disabled, enable clock */
if (!otg_is_active(transceiver))
otg_set_suspend(transceiver, 0);
ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1M);
if (__raw_readl(ctrl_base + OCP2SCP_TIMING_OFFSET) != 0x0000000F)
__raw_writel(0x00000000F, ctrl_base + OCP2SCP_TIMING_OFFSET);
read_val = __raw_readl(ctrl_base + USB2PHYCM_TRIM_OFFSET);
swcap_trim = (read_val & 0x00007F00) >> 8;
/* 0x4E(default) + 0x22(SWCAP_TRIM_OFFSET) = 0xF0*/
if (swcap_trim != (0x4E + swcap_trim_offset)) {
swcap_trim = 0x4E + swcap_trim_offset;
read_val &= ~0x00007F00;
read_val |= swcap_trim << 8;
read_val |= 0x00008000; /* USE_SW_TRIM = 1 */
__raw_writel(read_val, ctrl_base + USB2PHYCM_TRIM_OFFSET);
}
#ifndef CONFIG_USB_SWITCH_FSA9480
iounmap(ctrl_base);
#endif /* CONFIG_USB_SWITCH_FSA9480 */
}
static void musb_otg_init(struct musb *musb)
{
unsigned long flags = 0;
pm_runtime_get_sync(musb->controller);
/* reset musb controller */
#ifndef CONFIG_USB_SAMSUNG_OMAP_NORPM
musb_otg_core_reset(musb);
#endif
spin_lock_irqsave(&musb->lock, flags);
if (otg_is_active(musb->xceiv))
otg_set_suspend(musb->xceiv, 1);
otg_set_suspend(musb->xceiv, 0);
spin_unlock_irqrestore(&musb->lock, flags);
otg_init(musb->xceiv);
msleep(musb->otg_enum_delay);
omap2430_musb_set_vbus(musb, 1);
musb->otg_enum_delay = INIT_OTG_DELAY;
}
static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
{
u8 devctl;
unsigned long timeout = 1000;
int ret = 1;
/* HDRC controls CPEN, but beware current surges during device
* connect. They can trigger transient overcurrent conditions
* that must be ignored.
*/
if (!otg_is_active(musb->xceiv) && !is_on) {
dev_info(musb->controller, "otg is not active.\n");
return;
}
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
if (is_on) {
if (musb->xceiv->state == OTG_STATE_A_IDLE) {
/* start the session */
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
/*
* Wait for the musb to set as A device to enable the
* VBUS
*/
while (musb_readb(musb->mregs, MUSB_DEVCTL) & 0x80) {
cpu_relax();
if (!timeout) {
dev_err(musb->controller,
"configured as A device timeout");
ret = -EINVAL;
break;
}
mdelay(1);
timeout--;
}
if (ret && musb->xceiv->set_vbus)
otg_set_vbus(musb->xceiv, 1);
musb->xceiv->default_a = 1;
musb->vbus_reset_count = 0;
MUSB_HST_MODE(musb);
}
} else {
musb->is_active = 0;
/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
* jumping right to B_IDLE...
*/
musb->xceiv->default_a = 0;
musb->xceiv->state = OTG_STATE_B_IDLE;
devctl &= ~MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
MUSB_DEV_MODE(musb);
}
dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
