void tal_tx_beacon(frame_info_t *tx_frame)
{
tal_trx_status_t trx_status;
/* Set pointer to actual mpdu to be downloaded to the transceiver. */
uint8_t *tal_beacon_to_tx = tx_frame->mpdu;
/* Avoid that the beacon is transmitted while other transmision is on-going. */
if (tal_state == TAL_TX_AUTO)
{
Assert("trying to transmit beacon while ongoing transmission" == 0);
return;
}
/* Send the pre-created beacon frame to the transceiver. */
do
{
trx_status = set_trx_state(CMD_PLL_ON);
#if (_DEBUG_ > 1)
if (trx_status != PLL_ON)
{
Assert("PLL_ON failed for beacon transmission" == 0);
}
#endif
}
while (trx_status != PLL_ON);
// \TODO wait for talbeaconTxTime
pal_trx_irq_dis();
/* Toggle the SLP_TR pin triggering transmission. */
PAL_SLP_TR_HIGH();
PAL_WAIT_65_NS();
PAL_SLP_TR_LOW();
/*
* Send the frame to the transceiver.
* Note: The PhyHeader is the first byte of the frame to
* be sent to the transceiver and this contains the frame
* length.
* The actual length of the frame to be downloaded
* (parameter two of pal_trx_frame_write)
* is
* 1 octet frame length octet
* + n octets frame (i.e. value of frame_tx[0])
* + 1 extra octet (see datasheet)
* - 2 octets FCS
*/
pal_trx_frame_write(tal_beacon_to_tx, tal_beacon_to_tx[0]);
tal_beacon_transmission = true;
#ifndef NON_BLOCKING_SPI
pal_trx_irq_en();
#endif
#ifdef TX_OCTET_COUNTER
tal_tx_octet_cnt += PHY_OVERHEAD + LENGTH_FIELD_LEN + tal_beacon_to_tx[0];
#endif
}
/*
* \brief Perform a single ED measurement
*
* \return ed_value Result of the measurement
* If the build switch TRX_REG_RAW_VALUE is defined, the transceiver's
* register value is returned.
*/
uint8_t tfa_ed_sample(void)
{
uint8_t ed_value;
tal_trx_status_t trx_status;
/* Make sure that receiver is switched on. */
do
{
trx_status = set_trx_state(CMD_RX_ON);
}
while (trx_status != RX_ON);
/*
* Disable the transceiver interrupts to prevent frame reception
* while performing ED scan.
*/
pal_trx_irq_dis();
/*
* Initiate ED operation by writing any value into transceiver register
* PHY_ED_LEVEL.
*/
pal_trx_reg_write(RG_PHY_ED_LEVEL, 0x00);
/*
* Start timer for reading ED value from the transceiver after
* 140 microseconds.
*/
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(ED_SAMPLE_DURATION_SYM + 1));
/* Read the ED Value. */
ed_value = pal_trx_reg_read(RG_PHY_ED_LEVEL);
/* Clear IRQ register */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Enable reception agian */
pal_trx_irq_flag_clr();
pal_trx_irq_en();
/* Switch receiver off again */
set_trx_state(CMD_TRX_OFF);
#ifndef TRX_REG_RAW_VALUE
/*
* Scale ED result.
* Clip values to 0xFF if > -35dBm
*/
if (ed_value > CLIP_VALUE_REG)
{
ed_value = 0xFF;
}
else
{
ed_value = (uint8_t)(((uint16_t)ed_value * 0xFF) / CLIP_VALUE_REG);
}
#endif
return ed_value;
}
/**
* \brief Finalizes the CSMA procedure
*
* \param status Result of the slotted transmission
*/
static void tx_done(retval_t status)
{
#if (_DEBUG_ > 0)
switch (tal_state) {
case TAL_SLOTTED_CSMA:
case TAL_TX_BASIC:
break;
#if ((MAC_START_REQUEST_CONFIRM == 1) && (defined BEACON_SUPPORT))
case TAL_TX_BEACON:
Assert("unexpected tal_state TAL_TX_BEACON" == 0);
return;
/* break; */
#endif /* ((MAC_START_REQUEST_CONFIRM == 1) && (defined BEACON_SUPPORT)) */
default:
Assert("unexpected tal_state" == 0);
break;
}
#endif
#if (_DEBUG_ > 0)
if (pal_is_timer_running(TAL_CSMA_BEACON_LOSS_TIMER)) {
Assert("beacon lost timer is still running" == 0);
}
#endif
tal_state = TAL_IDLE;
tal_csma_state = CSMA_IDLE;
/*
* Restore the interrupt handler.
* Install a handler for the transceiver interrupt.
*/
pal_trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_reg_read(RG_IRQ_STATUS);
/* Check if a receive buffer is available. */
if (NULL != tal_rx_buffer) {
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
} else {
tal_rx_on_required = true;
}
pal_trx_irq_en();
/* debug pin to switch on: define ENABLE_DEBUG_PINS, pal_config.h */
PIN_CSMA_END();
tal_tx_frame_done_cb(status, mac_frame_ptr);
}
/**
* Function disabling the Timestamp IRQ as utilized for ranging.
*/
void rtb_tstamp_irq_exit(void)
{
TCC1_INTCTRLB = TC_CCAINTLVL_OFF_gc;
TCC1_CTRLB &= ~TC1_CCAEN_bm;
/* Clear status register. */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Enable main Trx IRQ. */
pal_trx_irq_en();
/* Re-enable all interrupts. */
pal_global_irq_enable();
}
/**
* \brief Transmits the frame over-the-air
*/
static void tx_frame(void)
{
tal_trx_status_t trx_status;
/*
* Trigger transmission
* In case of an ongoing reception,
* the incoming frame is handled first within ISR.
*/
do
{
trx_status = set_trx_state(CMD_TX_ARET_ON);
}
while (trx_status != TX_ARET_ON);
pal_trx_irq_dis();
/* Toggle the SLP_TR pin triggering transmission. */
PAL_SLP_TR_HIGH();
PAL_WAIT_65_NS();
PAL_SLP_TR_LOW();
/*
* Send the frame to the transceiver.
* Note: The PhyHeader is the first byte of the frame to
* be sent to the transceiver and this contains the frame
* length.
* The actual length of the frame to be downloaded
* (parameter two of pal_trx_frame_write)
* is
* 1 octet frame length octet
* + n octets frame (i.e. value of frame_tx[0])
* + 1 extra octet (see datasheet)
* - 2 octets FCS
*/
pal_trx_frame_write(tal_frame_to_tx, tal_frame_to_tx[0]);
tal_state = TAL_TX_AUTO;
#ifndef NON_BLOCKING_SPI
pal_trx_irq_en();
#endif
#ifdef TX_OCTET_COUNTER
tal_tx_octet_cnt += PHY_OVERHEAD + LENGTH_FIELD_LEN + tal_frame_to_tx[0];
#endif
}
/**
* @brief Switches the PLL on
*/
static void switch_pll_on(void)
{
trx_irq_reason_t irq_status;
uint32_t start_time, now;
/* Check if trx is in TRX_OFF; only from PLL_ON the following procedure is applicable */
if (pal_trx_bit_read(SR_TRX_STATUS) != TRX_OFF)
{
ASSERT("Switch PLL_ON failed, because trx is not in TRX_OFF" == 0);
return;
}
/* use the IRQ status register checking for the actual PLL status */
pal_trx_irq_dis();
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_PLL_LOCK); /* allow PLL lock IRQ only*/
pal_trx_reg_read(RG_IRQ_STATUS); /* clear PLL lock bit */
/* Switch PLL on */
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
/* Check if PLL has been locked. */
pal_get_current_time(&start_time);
while (1)
{
irq_status = (trx_irq_reason_t)pal_trx_reg_read(RG_IRQ_STATUS);
if (irq_status & TRX_IRQ_PLL_LOCK)
{
break; // PLL is locked now
}
/* Check if polling needs too much time. */
pal_get_current_time(&now);
if (pal_sub_time_us(now, start_time) > (10 * PLL_LOCK_TIME_US))
{
/* leave poll loop and throw assertion */
#if (DEBUG > 0)
ASSERT("PLL switch failed" == 0);
#endif
break;
}
}
pal_trx_irq_flag_clr();
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_TRX_END); /* enable TRX_END interrupt */
pal_trx_irq_en();
}
/**
* @brief Initializes the TAL
*
* This function is called to initialize the TAL. The transceiver is
* initialized, the TAL PIBs are set to their default values, and the TAL state
* machine is set to TAL_IDLE state.
*
* @return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
retval_t tal_init(void)
{
/* Init the PAL and by this means also the transceiver interface */
#ifdef ENABLE_RP
/*
* The ranging processor (RP) only performs a minimalistic
* initialization here.
*/
pal_basic_init();
#else /* !ENABLE_RP */
if (pal_init() != MAC_SUCCESS)
{
return FAILURE;
}
if (trx_init() != MAC_SUCCESS)
{
return FAILURE;
}
#if (EXTERN_EEPROM_AVAILABLE == 1)
pal_ps_get(EXTERN_EEPROM, EE_IEEE_ADDR, 8, &tal_pib.IeeeAddress);
#else
#if (USER_SIGN_AVAILABLE == 1)
pal_ps_get(USER_SIGNATURE, USER_SIGNATURES_START + 2, 8, &tal_pib.IeeeAddress);
//http://www.atmel.com/Images/Atmel-42172-Wireless-ZigBit-ATZB-X0-256-3-0-C_Datasheet.pdf
#else
pal_ps_get(INTERN_EEPROM, EE_IEEE_ADDR, 8, &tal_pib.IeeeAddress);
#endif
#endif
/*
* Do the reset stuff.
* Set the default PIBs.
* Generate random seed.
*/
if (internal_tal_reset(true) != MAC_SUCCESS)
{
return FAILURE;
}
#ifndef DISABLE_IEEE_ADDR_CHECK
/* Check if a valid IEEE address is available. */
/*
* This while loop is on purpose, since just in the
* rare case that such an address is randomly
* generated again, we must repeat this.
*/
while ((tal_pib.IeeeAddress == 0x0000000000000000) ||
(tal_pib.IeeeAddress == 0xFFFFFFFFFFFFFFFF))
{
/*
* In case no valid IEEE address is available, a random
* IEEE address will be generated to be able to run the
* applications for demonstration purposes.
* In production code this can be omitted.
*/
/*
* The proper seed for function rand() has already been generated
* in function tal_generate_rand_seed().
*/
uint8_t *ptr_pib = (uint8_t *)&tal_pib.IeeeAddress;
for (uint8_t i = 0; i < 8; i++)
{
*ptr_pib++ = (uint8_t)rand();
/*
* Note:
* Even if casting the 16 bit rand value back to 8 bit,
* and running the loop 8 timers (instead of only 4 times)
* may look cumbersome, it turns out that the code gets
* smaller using 8-bit here.
* And timing is not an issue at this place...
*/
}
}
#endif /* #ifndef DISABLE_IEEE_ADDR_CHECK */
#endif /* ENABLE_RP */
/*
* Configure interrupt handling.
* Install a handler for the transceiver interrupt.
*/
pal_trx_irq_init(trx_irq_handler_cb);
#ifndef ENABLE_RP
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#endif
#if ((defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP)) && (DISABLE_TSTAMP_IRQ == 0)
/* Configure time stamp interrupt. */
pal_trx_irq_init_tstamp(trx_irq_timestamp_handler_cb);
#ifndef ENABLE_RP
pal_trx_irq_en_tstamp(); /* Enable timestamp interrupt. */
#endif
#endif
/* Initialize the buffer management module and get a buffer to store received frames. */
bmm_buffer_init();
tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE);
#if DEBUG > 0
if (tal_rx_buffer == NULL)
{
return FAILURE;
}
#endif
/* Init incoming frame queue */
#ifdef ENABLE_QUEUE_CAPACITY
qmm_queue_init(&tal_incoming_frame_queue, TAL_INCOMING_FRAME_QUEUE_CAPACITY);
#else
qmm_queue_init(&tal_incoming_frame_queue);
#endif /* ENABLE_QUEUE_CAPACITY */
#ifdef ENABLE_TFA
tfa_init();
#endif
return MAC_SUCCESS;
} /* tal_init() */
void tal_tx_beacon(frame_info_t *tx_frame)
{
tal_trx_status_t trx_status;
/* Set pointer to actual mpdu to be downloaded to the transceiver. */
uint8_t *tal_beacon_to_tx = tx_frame->mpdu;
/*
* Avoid that the beacon is transmitted while transmitting
* a frame using slotted CSMA.
*/
if ((tal_csma_state == FRAME_SENDING_WITH_ACK) ||
(tal_csma_state == FRAME_SENDING_NO_ACK) ||
(tal_csma_state == WAITING_FOR_ACK)) {
Assert(
"trying to transmit beacon while ongoing transmission" ==
0);
return;
}
/* Send the pre-created beacon frame to the transceiver. */
/* debug pin to switch on: define ENABLE_DEBUG_PINS, pal_config.h */
PIN_BEACON_START();
/* \TODO wait for talbeaconTxTime */
do {
trx_status = set_trx_state(CMD_FORCE_PLL_ON);
#if (_DEBUG_ > 1)
if (trx_status != PLL_ON) {
Assert("PLL_ON failed for beacon transmission" == 0);
}
#endif
} while (trx_status != PLL_ON);
pal_trx_irq_dis();
/* Toggle the SLP_TR pin triggering transmission. */
PAL_SLP_TR_HIGH();
PAL_WAIT_65_NS();
PAL_SLP_TR_LOW();
/*
* Send the frame to the transceiver.
* Note: The PhyHeader is the first byte of the frame to
* be sent to the transceiver and this contains the frame
* length.
* The actual length of the frame to be downloaded
* (parameter two of pal_trx_frame_write)
* is
* 1 octet frame length octet
* + n octets frame (i.e. value of frame_tx[0])
* - 2 octets FCS
*/
pal_trx_frame_write(tal_beacon_to_tx, tal_beacon_to_tx[0] - 1);
#ifndef NON_BLOCKING_SPI
pal_trx_irq_en();
#endif
tal_state = TAL_TX_BEACON;
}
/*
* \brief Sends frame
*
* \param use_csma Flag indicating if CSMA is requested
* \param tx_retries Flag indicating if transmission retries are requested
* by the MAC layer
*/
void send_frame(csma_mode_t csma_mode, bool tx_retries)
{
tal_trx_status_t trx_status;
#ifdef BEACON_SUPPORT
/* Handle frame transmission in slotted CSMA via basic mode */
if (tal_csma_state != CSMA_IDLE) {
do {
trx_status = set_trx_state(CMD_PLL_ON);
} while (trx_status != PLL_ON);
tal_state = TAL_TX_BASIC;
} else
#endif
{
/* Configure tx according to tx_retries */
if (tx_retries) {
pal_trx_bit_write(SR_MAX_FRAME_RETRIES,
tal_pib.MaxFrameRetries);
} else {
pal_trx_bit_write(SR_MAX_FRAME_RETRIES, 0);
}
/* Configure tx according to csma usage */
if ((csma_mode == NO_CSMA_NO_IFS) ||
(csma_mode == NO_CSMA_WITH_IFS)) {
/*
* RF230B does not support "no" CSMA mode,
* therefore use shortest CSMA mode: CCA w/o backoff
*/
pal_trx_bit_write(SR_MIN_BE, 0x00);
pal_trx_bit_write(SR_MAX_CSMA_RETRIES, 0);
} else {
pal_trx_bit_write(SR_MIN_BE, tal_pib.MinBE);
pal_trx_bit_write(SR_MAX_CSMA_RETRIES,
tal_pib.MaxCSMABackoffs);
/*
* Handle interframe spacing
* Reduce IFS duration, since RF230B does CCA
*/
if (csma_mode == NO_CSMA_WITH_IFS) {
if (last_frame_length > aMaxSIFSFrameSize) {
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(
macMinLIFSPeriod_def -
CCA_DURATION_SYM)
- IRQ_PROCESSING_DLY_US -
PRE_TX_DURATION_US);
} else {
/*
* No delay required, since processing
*delay and CCA_DURATION_SYM
* delay the handling enough.
*/
}
}
}
do {
trx_status = set_trx_state(CMD_TX_ARET_ON);
} while (trx_status != TX_ARET_ON);
tal_state = TAL_TX_AUTO;
}
pal_trx_irq_dis();
/* Toggle the SLP_TR pin triggering transmission. */
PAL_SLP_TR_HIGH();
PAL_WAIT_65_NS();
PAL_SLP_TR_LOW();
/*
* Send the frame to the transceiver.
* Note: The PhyHeader is the first byte of the frame to
* be sent to the transceiver and this contains the frame
* length.
* The actual length of the frame to be downloaded
* (parameter two of pal_trx_frame_write)
* is
* 1 octet frame length octet
* + n octets frame (i.e. value of frame_tx[0])
* - 2 octets FCS
*/
pal_trx_frame_write(tal_frame_to_tx, tal_frame_to_tx[0] - 1);
#ifndef NON_BLOCKING_SPI
pal_trx_irq_en();
#endif
}
/**
* @brief Get the transceiver's supply voltage
*
* @return mv Milli Volt; 0 if below threshold, 0xFFFF if above threshold
*/
uint16_t tfa_get_batmon_voltage(void)
{
tal_trx_status_t previous_trx_status;
uint8_t vth_val;
uint16_t mv = 1; // 1 used as indicator flag
bool range;
previous_trx_status = tal_trx_status;
if (tal_trx_status == TRX_SLEEP)
{
set_trx_state(CMD_TRX_OFF);
}
/*
* Disable all trx interrupts.
* This needs to be done AFTER the transceiver has been woken up.
*/
pal_trx_irq_dis();
/* Check if supply voltage is within upper or lower range. */
pal_trx_bit_write(SR_BATMON_HR, BATMON_HR_HIGH);
pal_trx_bit_write(SR_BATMON_VTH, 0x00);
pal_timer_delay(5); /* Wait until Batmon has been settled. */
/* Check if supply voltage is within lower range */
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_NOT_VALID)
{
/* Lower range */
/* Check if supply voltage is below lower limit */
pal_trx_bit_write(SR_BATMON_HR, BATMON_HR_LOW);
pal_timer_delay(2); /* Wait until Batmon has been settled. */
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_NOT_VALID)
{
/* below lower limit */
mv = SUPPLY_VOLTAGE_BELOW_LOWER_LIMIT;
}
range = LOW;
}
else
{
/* Higher range */
/* Check if supply voltage is above upper limit */
pal_trx_bit_write(SR_BATMON_VTH, 0x0F);
pal_timer_delay(5); /* Wait until Batmon has been settled. */
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_VALID)
{
/* above upper limit */
mv = SUPPLY_VOLTAGE_ABOVE_UPPER_LIMIT;
}
range = HIGH;
}
/* Scan through the current range for the matching threshold. */
if (mv == 1) // 1 = indicates that voltage is within supported range
{
vth_val = 0x0F;
for (uint8_t i = 0; i < 16; i++)
{
pal_trx_bit_write(SR_BATMON_VTH, vth_val);
pal_timer_delay(2); /* Wait until Batmon has been settled. */
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_VALID)
{
break;
}
vth_val--;
}
/* Calculate voltage based on register value and range. */
if (range == HIGH)
{
mv = 2550 + (75 * vth_val);
}
else
{
mv = 1700 + (50 * vth_val);
}
}
pal_trx_reg_read(RG_IRQ_STATUS);
/*
* Enable all trx interrupts.
* This needs to be done BEFORE putting the transceiver back to slee.
*/
pal_trx_irq_en();
if (previous_trx_status == TRX_SLEEP)
{
set_trx_state(CMD_SLEEP);
}
return mv;
}
/*
* \brief Get the transceiver's supply voltage
*
* \return mv Milli Volt; 0 if below threshold, 0xFFFF if above threshold
*/
uint16_t tfa_get_batmon_voltage(void)
{
tal_trx_status_t previous_trx_status;
uint8_t vth_val;
uint8_t i;
uint16_t mv = 1; /* 1 used as indicator flag */
bool range;
previous_trx_status = tal_trx_status;
if (tal_trx_status == TRX_SLEEP) {
set_trx_state(CMD_TRX_OFF);
}
/*
* Disable all trx interrupts.
* This needs to be done AFTER the transceiver has been woken up.
*/
pal_trx_irq_dis();
/* Check if supply voltage is within lower range */
trx_bit_write(SR_BATMON_HR, BATMON_LOW_RANGE);
trx_bit_write(SR_BATMON_VTH, 0x0F);
pal_timer_delay(5); /* Wait until Batmon has been settled. */
if (trx_bit_read(SR_BATMON_OK) == BATMON_BELOW_THRES) {
/* Lower range */
/* Check if supply voltage is below lower limit */
trx_bit_write(SR_BATMON_VTH, 0);
pal_timer_delay(2); /* Wait until Batmon has been settled. */
if (trx_bit_read(SR_BATMON_OK) == BATMON_BELOW_THRES) {
/* below lower limit */
mv = SUPPLY_VOLTAGE_BELOW_LOWER_LIMIT;
}
range = LOW;
} else {
/* Higher range */
trx_bit_write(SR_BATMON_HR, BATMON_HIGH_RANGE);
/* Check if supply voltage is above upper limit */
trx_bit_write(SR_BATMON_VTH, 0x0F);
pal_timer_delay(5); /* Wait until Batmon has been settled. */
if (trx_bit_read(SR_BATMON_OK) == BATMON_ABOVE_THRES) {
/* above upper limit */
mv = SUPPLY_VOLTAGE_ABOVE_UPPER_LIMIT;
}
range = HIGH;
}
/* Scan through the current range for the matching threshold. */
if (mv == 1) {
vth_val = 0x0F;
for (i = 0; i < 16; i++) {
trx_bit_write(SR_BATMON_VTH, i);
pal_timer_delay(2); /* Wait until Batmon has been
* settled. */
if (trx_bit_read(SR_BATMON_OK) ==
BATMON_BELOW_THRES) {
if (i > 0) {
vth_val = i - 1;
} else {
vth_val = i;
}
break;
}
}
if (range == HIGH) {
mv = 2550 + (75 * vth_val);
} else {
mv = 1700 + (50 * vth_val);
}
}
trx_reg_read(RG_IRQ_STATUS);
/*
* Enable all trx interrupts.
* This needs to be done BEFORE putting the transceiver back to slee.
*/
pal_trx_irq_en();
if (previous_trx_status == TRX_SLEEP) {
set_trx_state(CMD_SLEEP);
}
return mv;
}
/**
* \brief Interrupt handler for ACK reception
*
* \param parameter Unused callback parameter
*/
static void ack_reception_handler_cb(void *parameter)
{
trx_irq_reason_t trx_irq_cause;
if (tal_csma_state == TX_DONE_NO_ACK) {
return; /* ack expiration timer has already been fired */
}
trx_irq_cause = (trx_irq_reason_t)pal_trx_reg_read(RG_IRQ_STATUS);
if (trx_irq_cause & TRX_IRQ_TRX_END) {
retval_t timer_status;
switch (tal_csma_state) {
case FRAME_SENDING_WITH_ACK:
set_trx_state(CMD_RX_ON);
timer_status
= pal_timer_start(TAL_ACK_WAIT_TIMER,
TAL_CONVERT_SYMBOLS_TO_US(
TAL_ACK_WAIT_DURATION_DEFAULT),
TIMEOUT_RELATIVE,
(FUNC_PTR)ack_timer_expiry_handler_cb,
NULL);
if (timer_status == MAC_SUCCESS) {
tal_csma_state = WAITING_FOR_ACK;
} else if (timer_status == PAL_TMR_ALREADY_RUNNING) {
tal_csma_state = WAITING_FOR_ACK;
} else {
tal_csma_state = TX_DONE_NO_ACK;
Assert("timer start failed" == 0);
}
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_TX_END();
PIN_ACK_WAITING_START();
break;
case WAITING_FOR_ACK:
{
uint8_t ack_frame[ACK_FRAME_LEN + LENGTH_FIELD_LEN];
/*
* Read the frame buffer, identify if this is an ACK
*frame,
* and get the sequence number.
* Üpload the frame from the transceiver.
*/
pal_trx_frame_read(ack_frame,
(ACK_FRAME_LEN +
LENGTH_FIELD_LEN));
/* Check if the uploaded frame is an ACK frame */
if ((ack_frame[1] & ACK_FRAME) != ACK_FRAME) {
/* The received frame is not an ACK frame */
return;
}
/* check CRC */
if (pal_trx_bit_read(SR_RX_CRC_VALID) != CRC16_VALID) {
return;
}
/* check the sequence number */
if (ack_frame[3] == tal_frame_to_tx[SEQ_NUMBER_POS]) {
/*
* If we are here, the ACK is valid and matches
* the transmitted sequence number.
*/
pal_timer_stop(TAL_ACK_WAIT_TIMER);
#if (_DEBUG_ > 0)
if (pal_is_timer_running(TAL_ACK_WAIT_TIMER)) {
Assert("Ack timer running" == 0);
}
#endif
/* restore the interrupt handler */
pal_trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en();
if (NULL != tal_rx_buffer) {
pal_trx_reg_write(RG_TRX_STATE,
CMD_RX_AACK_ON);
} else {
tal_rx_on_required = true;
}
/* debug pin to switch on: define
*ENABLE_DEBUG_PINS, pal_config.h */
PIN_ACK_OK_START();
if (ack_frame[1] & FCF_FRAME_PENDING) {
tal_csma_state = TX_DONE_FRAME_PENDING;
} else {
tal_csma_state = TX_DONE_SUCCESS;
}
/* debug pin to switch on: define
*ENABLE_DEBUG_PINS, pal_config.h */
PIN_ACK_OK_END();
PIN_ACK_WAITING_END();
}
}
break;
case FRAME_SENDING_NO_ACK:
/* Tx is done */
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_TX_END();
tal_csma_state = TX_DONE_SUCCESS;
break;
default:
Assert("unknown tal_csma_state" == 0);
break;
}
} else { /* other interrupt than TRX_END */
/* no interest in any other interrupt */
return;
}
parameter = parameter; /* Keep compiler happy. */
}
/**
* \brief Performs CCA twice
*/
static uint8_t perform_cca_twice(void)
{
tal_trx_status_t trx_status;
uint8_t cca_status;
uint8_t CW = 2;
uint32_t now_time_us;
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
(SLEEP_TO_TRX_OFF_US + CCA_PREPARATION_DURATION_US)) <
cca_starttime_us);
/* Ensure that trx is at least in TRX_OFF mode at this time. */
if (tal_trx_status == TRX_SLEEP) {
set_trx_state(CMD_TRX_OFF);
}
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
(PLL_LOCK_TIME_US + CCA_PREPARATION_DURATION_US)) <
cca_starttime_us);
/*
* Set trx to PLL_ON.
* If trx is busy and trx cannot be set to PLL_ON, assess channel as
*busy.
*/
if (set_trx_state(CMD_PLL_ON) != PLL_ON) {
return PHY_BUSY;
}
/* no interest in trx interrupts while doing CCA */
pal_trx_irq_dis();
/* do CCA twice */
do {
/* wait here until 16us before backoff boundary */
/* assume TRX is in PLL_ON */
do {
pal_get_current_time(&now_time_us);
} while (pal_add_time_us(now_time_us,
CCA_PRE_START_DURATION_US) <
cca_starttime_us);
set_trx_state(CMD_RX_ON);
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_CCA_START();
/* Start CCA by writing any dummy value to this register */
pal_trx_bit_write(SR_CCA_REQUEST, 1);
/* wait until CCA is done and get status */
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM));
do {
/* poll until CCA is really done; */
trx_status = (tal_trx_status_t)pal_trx_reg_read(
RG_TRX_STATUS);
} while ((trx_status & CCA_DONE_BIT) != CCA_DONE_BIT);
/* between both CCA switch trx to PLL_ON to reduce power
*consumption */
set_trx_state(CMD_PLL_ON);
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_CCA_END();
/* check if channel was idle or busy */
if (trx_status & CCA_STATUS_BIT) {
/* do next CCA at next backoff boundary */
cca_starttime_us = pal_add_time_us(cca_starttime_us,
TAL_CONVERT_SYMBOLS_TO_US(
aUnitBackoffPeriod));
CW--;
cca_status = PHY_IDLE;
} else { /* PHY busy */
cca_status = PHY_BUSY;
set_trx_state(CMD_RX_AACK_ON);
break; /* if channel is busy do no do CCA for the second
* time */
}
} while (CW > 0);
/*
* Keep trx ready for transmission if channel is idle.
* The transceiver is still in PLL_ON.
* If the channel is not idle, the trx handling is done in
*csma_backoff().
*/
/*
* Since we are not interested in any frames that might be received
* during CCA, reject any information that indicates a previous frame
* reception.
*/
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
pal_trx_irq_en();
return cca_status;
}
/**
* \brief State machine handling slotted CSMA
*/
void slotted_csma_state_handling(void)
{
switch (tal_csma_state) {
case BACKOFF_WAITING_FOR_CCA_TIMER:
break;
case BACKOFF_WAITING_FOR_BEACON:
/*
* Do not perform any operation and wait until the next beacon
* reception. If several beacons are not received, the beacon
*loss
* timer expires and stops the entire transaction.
*/
break;
case CSMA_HANDLE_BEACON:
/* debug pin to switch on: define ENABLE_DEBUG_PINS,
*pal_config.h */
PIN_WAITING_FOR_BEACON_END();
PIN_BEACON_LOSS_TIMER_END();
pal_timer_stop(TAL_CSMA_BEACON_LOSS_TIMER);
csma_backoff_calculation();
break;
case CSMA_ACCESS_FAILURE:
NB++;
BE++;
/* ensure that BE is no more than macMaxBE */
if (BE > tal_pib.MaxBE) { /* macMaxBE */
BE = tal_pib.MaxBE; /* macMaxBE */
}
if (NB > macMaxCSMABackoffs) {
/* terminate with channel access failure */
tx_done(MAC_CHANNEL_ACCESS_FAILURE);
} else {
/* restart backoff */
csma_backoff_calculation();
}
break;
case NO_BEACON_TRACKING:
/* terminate with channel access failure */
tx_done(MAC_CHANNEL_ACCESS_FAILURE);
break;
case FRAME_SENDING_WITH_ACK:
case FRAME_SENDING_NO_ACK:
/* waiting for end of frame transmission */
break;
case WAITING_FOR_ACK:
/* waiting for ACK reception */
break;
case TX_DONE_SUCCESS:
tx_done(MAC_SUCCESS);
break;
case TX_DONE_FRAME_PENDING:
tx_done(TAL_FRAME_PENDING);
break;
case TX_DONE_NO_ACK:
if (number_of_tx_retries < tal_pib.MaxFrameRetries) {
number_of_tx_retries++;
set_trx_state(CMD_RX_AACK_ON);
/*
* While continuing with CSMA, handle trx irq with
*regular isr.
* Install a handler for the transceiver interrupt.
*/
pal_trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_reg_read(RG_TRX_STATUS);
pal_trx_irq_en();
/*
* Start the entire CSMA procedure again,
* but do not reset the number of transmission attempts.
*/
BE++;
/* ensure that BE is no more than macMaxBE */
if (BE > tal_pib.MaxBE) { /* macMaxBE */
BE = tal_pib.MaxBE; /* macMaxBE */
}
NB = 0;
remaining_backoff_periods
= (uint8_t)(rand() & ((1 << BE) - 1));
csma_backoff_calculation();
} else {
tx_done(MAC_NO_ACK);
}
PIN_NO_ACK_END();
break;
default:
Assert("INVALID CSMA status" == 0);
break;
}
} /* csma_ca_state_handling() */
/*
* \brief Get the transceiver's supply voltage
*
* \return mv Milli Volt; 0 if below threshold, 0xFFFF if above threshold
*/
uint16_t tfa_get_batmon_voltage(void)
{
tal_trx_status_t previous_trx_status;
uint8_t vth_val;
uint8_t i;
uint16_t mv = 1; // 1 used as indicator flag
bool range;
pal_trx_irq_dis();
previous_trx_status = tal_trx_status;
if (tal_trx_status == TRX_SLEEP)
{
set_trx_state(CMD_TRX_OFF);
}
/* Check if supply voltage is within lower range */
pal_trx_bit_write(SR_BATMON_HR, BATMON_LOW_RANGE);
pal_trx_bit_write(SR_BATMON_VTH, 0x0F);
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_BELOW_THRES)
{
/* Lower range */
/* Check if supply voltage is below lower limit */
pal_trx_bit_write(SR_BATMON_VTH, 0);
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_BELOW_THRES)
{
/* below lower limit */
mv = SUPPLY_VOLTAGE_BELOW_LOWER_LIMIT;
}
range = LOW;
}
else
{
/* Higher range */
pal_trx_bit_write(SR_BATMON_HR, BATMON_HIGH_RANGE);
/* Check if supply voltage is above upper limit */
pal_trx_bit_write(SR_BATMON_VTH, 0x0F);
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_ABOVE_THRES)
{
/* above upper limit */
mv = SUPPLY_VOLTAGE_ABOVE_UPPER_LIMIT;
}
range = HIGH;
}
if (mv == 1)
{
vth_val = 0x0F;
for (i = 0; i < 16; i++)
{
pal_trx_bit_write(SR_BATMON_VTH, i);
if (pal_trx_bit_read(SR_BATMON_OK) == BATMON_BELOW_THRES)
{
if (i > 0)
{
vth_val = i - 1;
}
else
{
vth_val = i;
}
break;
}
}
if (range == HIGH)
{
mv = 2550 + (75 * vth_val);
}
else
{
mv = 1700 + (50 * vth_val);
}
}
pal_trx_reg_read(RG_IRQ_STATUS);
if (previous_trx_status == TRX_SLEEP)
{
set_trx_state(CMD_TRX_SLEEP);
}
pal_trx_irq_en();
return mv;
}
/**
* @brief Initializes the TAL
*
* This function is called to initialize the TAL. The transceiver is
* initialized, the TAL PIBs are set to their default values, and the TAL state
* machine is set to TAL_IDLE state.
*
* @return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
retval_t tal_init(void)
{
/* Init the PAL and by this means also the transceiver interface */
if (pal_init() != MAC_SUCCESS) {
return FAILURE;
}
/* Reset trx */
if (trx_reset(RFBOTH) != MAC_SUCCESS) {
return FAILURE;
}
/* Check if RF215 is connected */
if ((trx_reg_read( RG_RF_PN) != 0x34) ||
(trx_reg_read( RG_RF_VN) != 0x01)) {
return FAILURE;
}
/* Initialize trx */
trx_init();
if (tal_timer_init() != MAC_SUCCESS) {
return FAILURE;
}
/* Initialize the buffer management */
bmm_buffer_init();
/* Configure both trx and set default PIB values */
for (uint8_t trx_id = 0; trx_id < NUM_TRX; trx_id++) {
/* Configure transceiver */
trx_config((trx_id_t)trx_id);
#ifdef RF215V1
/* Calibrate LO */
calibrate_LO((trx_id_t)trx_id);
#endif
/* Set the default PIB values */
init_tal_pib((trx_id_t)trx_id); /* see 'tal_pib.c' */
calculate_pib_values((trx_id_t)trx_id);
/*
* Write all PIB values to the transceiver
* that are needed by the transceiver itself.
*/
write_all_tal_pib_to_trx((trx_id_t)trx_id); /* see 'tal_pib.c'
**/
config_phy((trx_id_t)trx_id);
tal_rx_buffer[trx_id] = bmm_buffer_alloc(LARGE_BUFFER_SIZE);
if (tal_rx_buffer[trx_id] == NULL) {
return FAILURE;
}
/* Init incoming frame queue */
qmm_queue_init(&tal_incoming_frame_queue[trx_id]);
tal_state[trx_id] = TAL_IDLE;
tx_state[trx_id] = TX_IDLE;
}
/* Init seed of rand() */
tal_generate_rand_seed();
#ifndef DISABLE_IEEE_ADDR_CHECK
for (uint8_t trx_id = 0; trx_id < 2; trx_id++) {
/* Check if a valid IEEE address is available. */
/*
* This while loop is on purpose, since just in the
* rare case that such an address is randomly
* generated again, we must repeat this.
*/
while ((tal_pib[trx_id].IeeeAddress == 0x0000000000000000) ||
(tal_pib[trx_id].IeeeAddress ==
((uint64_t)-1))) {
/*
* In case no valid IEEE address is available, a random
* IEEE address will be generated to be able to run the
* applications for demonstration purposes.
* In production code this can be omitted.
*/
/*
* The proper seed for function rand() has already been
*generated
* in function tal_generate_rand_seed().
*/
uint8_t *ptr_pib
= (uint8_t *)&tal_pib[trx_id].IeeeAddress;
for (uint8_t i = 0; i < 8; i++) {
*ptr_pib++ = (uint8_t)rand();
/*
* Note:
* Even if casting the 16 bit rand value back to
*8 bit,
* and running the loop 8 timers (instead of
*only 4 times)
* may look cumbersome, it turns out that the
*code gets
* smaller using 8-bit here.
* And timing is not an issue at this place...
*/
}
}
}
#endif
#ifdef IQ_RADIO
/* Init BB IRQ handler */
pal_trx_irq_flag_clr(RF215_BB);
trx_irq_init(RF215_BB, bb_irq_handler_cb);
pal_trx_irq_en(RF215_BB);
/* Init RF IRQ handler */
pal_trx_irq_flag_clr(RF215_RF);
trx_irq_init(RF215_RF, rf_irq_handler_cb);
pal_trx_irq_en(RF215_RF);
#else
/*
* Configure interrupt handling.
* Install a handler for the radio and the baseband interrupt.
*/
pal_trx_irq_flag_clr();
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#endif
#if ((defined SUPPORT_FSK) && (defined SUPPORT_MODE_SWITCH))
init_mode_switch();
#endif
return MAC_SUCCESS;
} /* tal_init() */
/*
* \brief Perform a CCA
*
* This function performs a CCA request.
*
* \return phy_enum_t PHY_IDLE or PHY_BUSY
*/
phy_enum_t tfa_cca_perform(void)
{
tal_trx_status_t trx_status;
uint8_t cca_status;
/* Ensure that trx is not in SLEEP for register access */
do
{
trx_status = set_trx_state(CMD_TRX_OFF);
}
while (trx_status != TRX_OFF);
// no interest in trx interrupts while doing CCA
pal_trx_irq_dis();
/* Set trx to rx mode. */
do
{
trx_status = set_trx_state(CMD_RX_ON);
}
while (trx_status != RX_ON);
/* Start CCA by writing any dummy value to this register */
pal_trx_bit_write(SR_CCA_REQUEST, 1);
/* wait until CCA is done */
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(CCA_DURATION_SYM));
do
{
/*
* Poll until CCA is really done.
* Do NOT use bit read here!
*/
trx_status = (tal_trx_status_t)pal_trx_reg_read(RG_TRX_STATUS);
}
while ((trx_status & CCA_DONE_BIT) != CCA_DONE_BIT);
set_trx_state(CMD_TRX_OFF);
/* Check if channel was idle or busy. */
if (trx_status & CCA_STATUS_BIT)
{
cca_status = PHY_IDLE;
}
else
{
cca_status = PHY_BUSY;
}
/*
* Since we are not interested in any frames that might be received
* during CCA, reject any information that indicates a previous frame
* reception.
*/
pal_trx_reg_read(RG_IRQ_STATUS);
pal_trx_irq_flag_clr();
pal_trx_irq_en();
return (phy_enum_t)cca_status;
}
/*
* \brief Sets transceiver state
*
* \param trx_cmd needs to be one of the trx commands
*
* \return current trx state
*/
tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd)
{
if (tal_trx_status == TRX_SLEEP) {
/*
* Since the wake-up procedure relies on the Awake IRQ and
* the global interrupts may be disabled at this point of time,
* we need to make sure that the global interrupts are enabled
* during wake-up procedure.
* Once the TRX is awake, the original state of the global
* interrupts
* will be restored.
*/
/* Reset wake-up interrupt flag. */
if (CMD_SLEEP == trx_cmd) {
return TRX_SLEEP;
}
tal_awake_end_flag = false;
/* Set callback function for the awake interrupt. */
trx_irq_init((FUNC_PTR)trx_irq_awake_handler_cb);
/* The pending transceiver interrupts on the microcontroller are
* cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
/* Save current state of global interrupts. */
ENTER_CRITICAL_REGION();
/* Force enabling of global interrupts. */
ENABLE_GLOBAL_IRQ();
/* Leave trx sleep mode. */
TRX_SLP_TR_LOW();
/* Poll wake-up interrupt flag until set within ISR. */
while (!tal_awake_end_flag) {
}
/* Restore original state of global interrupts. */
LEAVE_CRITICAL_REGION();
/* Clear existing interrupts */
trx_reg_read(RG_IRQ_STATUS);
/* Re-install default IRQ handler for main interrupt. */
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
/* Re-enable TRX_END interrupt */
trx_reg_write(RG_IRQ_MASK, TRX_IRQ_DEFAULT);
#if (ANTENNA_DIVERSITY == 1)
/* Enable antenna diversity. */
trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE);
#endif
if ((trx_cmd == CMD_TRX_OFF) ||
(trx_cmd == CMD_FORCE_TRX_OFF)) {
tal_trx_status = TRX_OFF;
return TRX_OFF;
}
}
switch (trx_cmd) { /* requested state */
case CMD_SLEEP:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
#if (ANTENNA_DIVERSITY == 1)
/* Disable antenna diversity: sets pulls */
trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE);
#endif
#ifndef SW_CONTROLLED_CSMA
{
uint16_t rand_value;
/*
* Init the SEED value of the CSMA backoff algorithm.
*/
rand_value = (uint16_t)rand();
trx_reg_write(RG_CSMA_SEED_0, (uint8_t)rand_value);
trx_bit_write(SR_CSMA_SEED_1,
(uint8_t)(rand_value >> 8));
}
#endif
/* Clear existing interrupts */
trx_reg_read(RG_IRQ_STATUS);
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
PAL_WAIT_1_US();
TRX_SLP_TR_HIGH();
pal_timer_delay(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES);
tal_trx_status = TRX_SLEEP;
return TRX_SLEEP; /* transceiver register cannot be read during
* TRX_SLEEP */
case CMD_TRX_OFF:
switch (tal_trx_status) {
case TRX_OFF:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_FORCE_TRX_OFF:
switch (tal_trx_status) {
case TRX_OFF:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_PLL_ON:
switch (tal_trx_status) {
case PLL_ON:
break;
case TRX_OFF:
switch_pll_on();
break;
case RX_ON:
case RX_AACK_ON:
case TX_ARET_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_FORCE_PLL_ON:
switch (tal_trx_status) {
case TRX_OFF:
switch_pll_on();
break;
case PLL_ON:
break;
default:
trx_reg_write(RG_TRX_STATE, CMD_FORCE_PLL_ON);
break;
}
break;
case CMD_RX_ON:
switch (tal_trx_status) {
case RX_ON:
break;
case PLL_ON:
case RX_AACK_ON:
case TX_ARET_ON:
trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_RX_AACK_ON:
switch (tal_trx_status) {
case RX_AACK_ON:
break;
case TX_ARET_ON:
case PLL_ON:
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); /* state change from TRX_OFF to
* RX_AACK_ON can be done directly, too
**/
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case RX_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
/* check if state change could be applied */
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
if (tal_trx_status != PLL_ON) {
return tal_trx_status;
}
trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
case CMD_TX_ARET_ON:
switch (tal_trx_status) {
case TX_ARET_ON:
break;
case PLL_ON:
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case RX_ON:
case RX_AACK_ON:
trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
/* check if state change could be applied */
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
if (tal_trx_status != PLL_ON) {
return tal_trx_status;
}
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); /* state change from TRX_OFF to
* TX_ARET_ON can be done directly, too
**/
trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
Assert("state transition not handled" == 0);
break;
}
break;
default:
/* CMD_NOP, CMD_TX_START */
Assert("trx command not handled" == 0);
break;
}
do {
tal_trx_status = (tal_trx_status_t)trx_bit_read(
SR_TRX_STATUS);
} while (tal_trx_status == STATE_TRANSITION_IN_PROGRESS);
return tal_trx_status;
} /* set_trx_state() */
/*
* \brief Sends frame using trx features to handle CSMA and re-transmissions
*
* \param use_csma Flag indicating if CSMA is requested
* \param tx_retries Flag indicating if transmission retries are requested
* by the MAC layer
*/
void send_frame(csma_mode_t csma_mode, bool tx_retries)
{
tal_trx_status_t trx_status;
/* Configure tx according to tx_retries */
if (tx_retries) {
trx_bit_write(SR_MAX_FRAME_RETRIES,
tal_pib.MaxFrameRetries);
} else {
trx_bit_write(SR_MAX_FRAME_RETRIES, 0);
}
/* Configure tx according to csma usage */
if ((csma_mode == NO_CSMA_NO_IFS) || (csma_mode == NO_CSMA_WITH_IFS)) {
trx_bit_write(SR_MAX_CSMA_RETRIES, 7); /* immediate
* transmission */
} else {
trx_bit_write(SR_MAX_CSMA_RETRIES, tal_pib.MaxCSMABackoffs);
}
do {
trx_status = set_trx_state(CMD_TX_ARET_ON);
} while (trx_status != TX_ARET_ON);
pal_trx_irq_dis();
/* Handle interframe spacing */
if (csma_mode == NO_CSMA_WITH_IFS) {
if (last_frame_length > aMaxSIFSFrameSize) {
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(
macMinLIFSPeriod_def)
- IRQ_PROCESSING_DLY_US -
PRE_TX_DURATION_US);
last_frame_length = 0;
} else {
pal_timer_delay(TAL_CONVERT_SYMBOLS_TO_US(
macMinSIFSPeriod_def)
- IRQ_PROCESSING_DLY_US -
PRE_TX_DURATION_US);
last_frame_length = 0;
}
}
/* Toggle the SLP_TR pin triggering transmission. */
TRX_SLP_TR_HIGH();
PAL_WAIT_65_NS();
TRX_SLP_TR_LOW();
/*
* Send the frame to the transceiver.
* Note: The PhyHeader is the first byte of the frame to
* be sent to the transceiver and this contains the frame
* length.
* The actual length of the frame to be downloaded
* (parameter two of trx_frame_write)
* is
* 1 octet frame length octet
* + n octets frame (i.e. value of frame_tx[0])
* - 2 octets FCS
*/
trx_frame_write(tal_frame_to_tx, tal_frame_to_tx[0] - 1);
tal_state = TAL_TX_AUTO;
#ifndef NON_BLOCKING_SPI
pal_trx_irq_en();
#endif
#ifdef TX_OCTET_COUNTER
tal_tx_octet_cnt += PHY_OVERHEAD + LENGTH_FIELD_LEN + frame_tx[0];
#endif
}
/*
* \brief Resets TAL state machine and sets the default PIB values if requested
*
* \param set_default_pib Defines whether PIB values need to be set
* to its default values
*
* \return MAC_SUCCESS if the transceiver state is changed to TRX_OFF
* FAILURE otherwise
*/
retval_t tal_reset(bool set_default_pib)
{
/*
* Do the reset stuff.
* Set the default PIBs depending on the given parameter
* set_default_pib.
* Do NOT generate random seed again.
*/
if (internal_tal_reset(set_default_pib) != MAC_SUCCESS) {
return FAILURE;
}
ENTER_CRITICAL_REGION();
tal_timers_stop();
LEAVE_CRITICAL_REGION();
/* Clear TAL Incoming Frame queue and free used buffers. */
while (tal_incoming_frame_queue.size > 0) {
buffer_t *frame = qmm_queue_remove(&tal_incoming_frame_queue,
NULL);
if (NULL != frame) {
bmm_buffer_free(frame);
}
}
#ifdef ENABLE_TFA
tfa_reset(set_default_pib);
#endif
/*
* Configure interrupt handling.
* Install a handler for the transceiver interrupt.
*/
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
/* The pending transceiver interrupts on the microcontroller are
* cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#ifdef ENABLE_FTN_PLL_CALIBRATION
{
/* Handle PLL calibration and filter tuning. */
retval_t timer_status;
/* Calibration timer has already been stopped within this
* function. */
/* Start periodic calibration timer.*/
timer_status = pal_timer_start(TAL_CALIBRATION,
TAL_CALIBRATION_TIMEOUT_US,
TIMEOUT_RELATIVE,
(FUNC_PTR)calibration_timer_handler_cb,
NULL);
if (timer_status != MAC_SUCCESS) {
Assert("PLL calibration timer start problem" == 0);
}
}
#endif /* ENABLE_FTN_PLL_CALIBRATION */
return MAC_SUCCESS;
}
/*
* \brief Initializes the TAL
*
* This function is called to initialize the TAL. The transceiver is
* initialized, the TAL PIBs are set to their default values, and the TAL state
* machine is set to TAL_IDLE state.
*
* \return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
retval_t tal_init(void)
{
/* Init the PAL and by this means also the transceiver interface */
if (pal_init() != MAC_SUCCESS) {
return FAILURE;
}
if (trx_init() != MAC_SUCCESS) {
return FAILURE;
}
if (tal_timer_init() != MAC_SUCCESS) {
return FAILURE;
}
#ifdef ENABLE_STACK_NVM
pal_ps_get(INTERN_EEPROM, EE_IEEE_ADDR, 8, &tal_pib.IeeeAddress);
#endif
/*
* Do the reset stuff.
* Set the default PIBs.
* Generate random seed.
*/
if (internal_tal_reset(true) != MAC_SUCCESS) {
return FAILURE;
}
#ifndef DISABLE_IEEE_ADDR_CHECK
/* Check if a valid IEEE address is available. */
/*
* This while loop is on purpose, since just in the
* rare case that such an address is randomly
* generated again, we must repeat this.
*/
uint64_t invalid_ieee_address;
memset((uint8_t *)&invalid_ieee_address, 0xFF,
sizeof(invalid_ieee_address));
while ((tal_pib.IeeeAddress == 0x0000000000000000) ||
(tal_pib.IeeeAddress == invalid_ieee_address)) {
/*
* In case no valid IEEE address is available, a random
* IEEE address will be generated to be able to run the
* applications for demonstration purposes.
* In production code this can be omitted.
*/
/*
* The proper seed for function rand() has already been
* generated
* in function tal_generate_rand_seed().
*/
uint8_t *ptr_pib = (uint8_t *)&tal_pib.IeeeAddress;
for (uint8_t i = 0; i < 8; i++) {
*ptr_pib++ = (uint8_t)rand();
/*
* Note:
* Even if casting the 16 bit rand value back to 8 bit,
* and running the loop 8 timers (instead of only 4
* times)
* may look cumbersome, it turns out that the code gets
* smaller using 8-bit here.
* And timing is not an issue at this place...
*/
}
}
#endif /* #ifndef DISABLE_IEEE_ADDR_CHECK */
#ifdef ENABLE_STACK_NVM
pal_ps_set(EE_IEEE_ADDR, 8, &tal_pib.IeeeAddress);
#endif
/*
* Configure interrupt handling.
* Install a handler for the main transceiver interrupt.
*/
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en(); /* Enable main transceiver interrupt. */
#if ((defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP)) && \
(DISABLE_TSTAMP_IRQ == 0)
/* Configure time stamp interrupt.
* The timestamping is only required for
* - beaconing networks or if timestamping is explicitly enabled,
* - and if the time stamp interrupt is not explicitly disabled.
*/
pal_trx_irq_init_tstamp((FUNC_PTR)trx_irq_timestamp_handler_cb);
pal_trx_irq_en_tstamp(); /* Enable timestamp interrupt. */
#endif
/* Initialize the buffer management module and get a buffer to store
* reveived frames. */
bmm_buffer_init();
tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE);
/* Init incoming frame queue */
#ifdef ENABLE_QUEUE_CAPACITY
qmm_queue_init(&tal_incoming_frame_queue,
TAL_INCOMING_FRAME_QUEUE_CAPACITY);
#else
qmm_queue_init(&tal_incoming_frame_queue);
#endif /* ENABLE_QUEUE_CAPACITY */
#ifdef ENABLE_TFA
tfa_init();
#endif
return MAC_SUCCESS;
} /* tal_init() */
/**
* @brief Resets TAL state machine and sets the default PIB values if requested
*
* @param trx_id Transceiver identifier
* @param set_default_pib Defines whether PIB values need to be set
* to its default values
*
* @return
* - @ref MAC_SUCCESS if the transceiver state is changed to TRX_OFF
* - @ref FAILURE otherwise
* @ingroup apiTalApi
*/
retval_t tal_reset(trx_id_t trx_id, bool set_default_pib)
{
rf_cmd_state_t previous_trx_state[NUM_TRX];
previous_trx_state[RF09] = trx_state[RF09];
previous_trx_state[RF24] = trx_state[RF24];
/* Reset the actual device or part of the device */
if (trx_reset(trx_id) != MAC_SUCCESS) {
return FAILURE;
}
/* Init Trx if necessary, e.g. trx was in deep sleep */
if (((previous_trx_state[RF09] == RF_SLEEP) &&
(previous_trx_state[RF24] == RF_SLEEP)) ||
(trx_id == RFBOTH)) {
trx_init(); /* Initialize generic trx functionality */
}
if (trx_id == RFBOTH) {
for (uint8_t i = 0; i < NUM_TRX; i++) {
/* Clean TAL and removed any pending tasks */
cleanup_tal((trx_id_t)i);
/* Configure the transceiver register values. */
trx_config((trx_id_t)i);
if (set_default_pib) {
/* Set the default PIB values */
init_tal_pib((trx_id_t)i); /* see 'tal_pib.c' */
calculate_pib_values(trx_id);
} else {
/* nothing to do - the current TAL PIB attribute
*values are used */
}
write_all_tal_pib_to_trx((trx_id_t)i); /* see
*'tal_pib.c' */
config_phy((trx_id_t)i);
/* Reset TAL variables. */
tal_state[(trx_id_t)i] = TAL_IDLE;
tx_state[(trx_id_t)i] = TX_IDLE;
#ifdef ENABLE_FTN_PLL_CALIBRATION
/* Stop FTN timer */
stop_ftn_timer((trx_id_t)i);
#endif /* ENABLE_FTN_PLL_CALIBRATION */
}
} else {
/* Maintain other trx */
trx_id_t other_trx_id;
if (trx_id == RF09) {
other_trx_id = RF24;
} else {
other_trx_id = RF09;
}
if (tal_state[other_trx_id] == TAL_SLEEP) {
/* Switch other trx back to sleep again */
uint16_t reg_offset = RF_BASE_ADDR_OFFSET *
other_trx_id;
#ifdef IQ_RADIO
pal_dev_reg_write(RF215_BB, reg_offset + RG_RF09_CMD,
RF_SLEEP);
pal_dev_reg_write(RF215_RF, reg_offset + RG_RF09_CMD,
RF_SLEEP);
#else
trx_reg_write(reg_offset + RG_RF09_CMD, RF_SLEEP);
#endif
TAL_RF_IRQ_CLR_ALL(trx_id);
}
/* Clean TAL and removed any pending tasks */
cleanup_tal(trx_id);
/* Configure the transceiver register values. */
trx_config(trx_id);
if (set_default_pib) {
/* Set the default PIB values */
init_tal_pib(trx_id); /* see 'tal_pib.c' */
calculate_pib_values(trx_id);
} else {
/* nothing to do - the current TAL PIB attribute values
*are used */
}
write_all_tal_pib_to_trx(trx_id); /* see 'tal_pib.c' */
config_phy(trx_id);
/* Reset TAL variables. */
tal_state[trx_id] = TAL_IDLE;
tx_state[trx_id] = TX_IDLE;
#ifdef ENABLE_FTN_PLL_CALIBRATION
/* Stop FTN timer */
stop_ftn_timer(trx_id);
#endif /* ENABLE_FTN_PLL_CALIBRATION */
}
/*
* Configure interrupt handling.
* Install a handler for the transceiver interrupt.
*/
#ifdef IQ_RADIO
trx_irq_init(RF215_BB, bb_irq_handler_cb);
trx_irq_init(RF215_RF, rf_irq_handler_cb);
pal_trx_irq_en(RF215_BB); /* Enable transceiver main interrupt. */
pal_trx_irq_en(RF215_RF); /* Enable transceiver main interrupt. */
#else
trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
#endif
return MAC_SUCCESS;
}
/**
* @brief Sets transceiver state
*
* @param trx_cmd needs to be one of the trx commands
*
* @return current trx state
*/
tal_trx_status_t set_trx_state(trx_cmd_t trx_cmd)
{
if (tal_trx_status == TRX_SLEEP)
{
/*
* Since the wake-up procedure relies on the Awake IRQ and
* the global interrupts may be disabled at this point of time,
* we need to make sure that the global interrupts are enabled
* during wake-up procedure.
* Once the TRX is awake, the original state of the global interrupts
* will be restored.
*/
/* Reset wake-up interrupt flag. */
tal_awake_end_flag = false;
/* Set callback function for the awake interrupt. */
pal_trx_irq_init(trx_irq_awake_handler_cb);
/* The pending transceiver interrupts on the microcontroller are cleared. */
pal_trx_irq_flag_clr();
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
/* Save current state of global interrupts. */
ENTER_CRITICAL_REGION();
/* Force enabling of global interrupts. */
ENABLE_GLOBAL_IRQ();
/* Leave trx sleep mode. */
PAL_SLP_TR_LOW();
/* Poll wake-up interrupt flag until set within ISR. */
while (!tal_awake_end_flag);
/* Restore original state of global interrupts. */
LEAVE_CRITICAL_REGION();
/* Clear existing interrupts */
pal_trx_reg_read(RG_IRQ_STATUS);
/* Re-install default IRQ handler for main interrupt. */
pal_trx_irq_init(trx_irq_handler_cb);
/* Re-enable TRX_END interrupt */
pal_trx_reg_write(RG_IRQ_MASK, TRX_IRQ_DEFAULT);
#if (ANTENNA_DIVERSITY == 1)
/* Enable antenna diversity. */
pal_trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_ENABLE);
#endif
#ifdef EXT_RF_FRONT_END_CTRL
/* Enable RF front end control */
pal_trx_bit_write(SR_PA_EXT_EN, 1);
#endif
tal_trx_status = TRX_OFF;
if ((trx_cmd == CMD_TRX_OFF) || (trx_cmd == CMD_FORCE_TRX_OFF))
{
return TRX_OFF;
}
}
#ifdef ENABLE_DEEP_SLEEP
else if (tal_trx_status == TRX_DEEP_SLEEP)
{
/* Leave trx sleep mode. */
PAL_SLP_TR_LOW();
/* Check if trx has left deep sleep. */
tal_trx_status_t trx_state;
do
{
trx_state = (tal_trx_status_t)pal_trx_reg_read(RG_TRX_STATUS);
}
while (trx_state != TRX_OFF);
tal_trx_status = TRX_OFF;
/* Using deep sleep, the transceiver's registers need to be restored. */
trx_config();
/*
* Write all PIB values to the transceiver
* that are needed by the transceiver itself.
*/
write_all_tal_pib_to_trx(); /* implementation can be found in 'tal_pib.c' */
if ((trx_cmd == CMD_TRX_OFF) || (trx_cmd == CMD_FORCE_TRX_OFF))
{
return TRX_OFF;
}
}
#endif
switch (trx_cmd) /* requested state */
{
case CMD_SLEEP:
#ifdef ENABLE_DEEP_SLEEP
/* Fall through. */
case CMD_DEEP_SLEEP:
#endif
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
#if (ANTENNA_DIVERSITY == 1)
/*
* Disable antenna diversity: to reduce the power consumption or
* avoid leakage current of an external RF switch during SLEEP.
*/
pal_trx_bit_write(SR_ANT_EXT_SW_EN, ANT_EXT_SW_DISABLE);
#endif
#ifdef EXT_RF_FRONT_END_CTRL
/* Disable RF front end control */
pal_trx_bit_write(SR_PA_EXT_EN, 0);
#endif
/* Clear existing interrupts */
pal_trx_reg_read(RG_IRQ_STATUS);
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
#ifdef ENABLE_DEEP_SLEEP
if (trx_cmd == CMD_DEEP_SLEEP)
{
pal_trx_reg_write(RG_TRX_STATE, CMD_PREP_DEEP_SLEEP);
tal_trx_status = TRX_DEEP_SLEEP;
}
else
{
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
tal_trx_status = TRX_SLEEP;
}
#else
/*
* Enable Awake_end interrupt.
* This is used for save wake-up from sleep later.
*/
pal_trx_bit_write(SR_IRQ_MASK, TRX_IRQ_4_CCA_ED_DONE);
tal_trx_status = TRX_SLEEP;
#endif
PAL_WAIT_1_US();
PAL_SLP_TR_HIGH();
pal_timer_delay(TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES);
/* Transceiver register cannot be read during TRX_SLEEP or DEEP_SLEEP. */
return tal_trx_status;
case CMD_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_FORCE_TRX_OFF:
switch (tal_trx_status)
{
case TRX_OFF:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
PAL_WAIT_1_US();
break;
}
break;
case CMD_PLL_ON:
switch (tal_trx_status)
{
case PLL_ON:
break;
case TRX_OFF:
switch_pll_on();
break;
case RX_ON:
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_FORCE_PLL_ON:
switch (tal_trx_status)
{
case TRX_OFF:
switch_pll_on();
break;
case PLL_ON:
break;
default:
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_PLL_ON);
break;
}
break;
case CMD_RX_ON:
switch (tal_trx_status)
{
case RX_ON:
break;
case PLL_ON:
case RX_AACK_ON:
case TX_ARET_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on();
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_RX_AACK_ON:
switch (tal_trx_status)
{
case RX_AACK_ON:
break;
case TX_ARET_ON:
case PLL_ON:
case RX_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); // state change from TRX_OFF to RX_AACK_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_RX_AACK_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
case CMD_TX_ARET_ON:
switch (tal_trx_status)
{
case TX_ARET_ON:
break;
case PLL_ON:
case RX_ON:
case RX_AACK_ON:
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case TRX_OFF:
switch_pll_on(); // state change from TRX_OFF to TX_ARET_ON can be done directly, too
pal_trx_reg_write(RG_TRX_STATE, CMD_TX_ARET_ON);
PAL_WAIT_1_US();
break;
case BUSY_RX:
case BUSY_TX:
case BUSY_RX_AACK:
case BUSY_TX_ARET:
/* do nothing if trx is busy */
break;
default:
ASSERT("state transition not handled" == 0);
break;
}
break;
default:
/* CMD_NOP, CMD_TX_START */
ASSERT("trx command not handled" == 0);
break;
}
do
{
tal_trx_status = (tal_trx_status_t)pal_trx_bit_read(SR_TRX_STATUS);
}
while (tal_trx_status == STATE_TRANSITION_IN_PROGRESS);
return tal_trx_status;
} /* set_trx_state() */
/*
* \brief Initializes the TAL
*
* This function is called to initialize the TAL. The transceiver is
* initialized, the TAL PIBs are set to their default values, and the TAL state
* machine is set to TAL_IDLE state.
*
* \return MAC_SUCCESS if the transceiver state is changed to TRX_OFF and the
* current device part number and version number are correct;
* FAILURE otherwise
*/
retval_t tal_init(void)
{
/* Init the PAL and by this means also the transceiver interface */
if (pal_init() != MAC_SUCCESS) {
return FAILURE;
}
if (trx_init() != MAC_SUCCESS) {
return FAILURE;
}
if (tal_timer_init() != MAC_SUCCESS) {
return FAILURE;
}
#ifdef ENABLE_STACK_NVM
pal_ps_get(INTERN_EEPROM, EE_IEEE_ADDR, 8, &tal_pib.IeeeAddress);
#endif
/*
* For systems including the AT86RF230B the random seed generation
* cannot be done using a dedicated hardware feature.
* Therefore all random seed generation needs to be done by special
* means (e.g. utilization of ADC) that generate a random value only
* within a certain range.
*
* In case the node already has a valid IEEE address (i.e. an IEEE
* address which is different from 0x0000000000000000 or
* 0xFFFFFFFFFFFFFFFF), this IEEE address (the lower 16 bit)
* shall be used as seed for srand(), since each node should have a
*unique
* IEEE address.
* In this case srand() is called directly and function
*tal_generate_rand_seed()
* is not called.
*
* Note: This behaviour is different in all other TALs, since in these
* cases the seed for srand() is always generated based on transceiver
* hardware support.
*/
#ifndef DISABLE_IEEE_ADDR_CHECK
if ((tal_pib.IeeeAddress == 0x0000000000000000) ||
(tal_pib.IeeeAddress == 0xFFFFFFFFFFFFFFFF)
) {
/*
* Generate a seed for the random number generator in function
*rand().
* This is required (for example) as seed for the CSMA-CA
*algorithm.
*/
tal_generate_rand_seed();
/*
* Now that we have generated a random seed, we can generate a
*random
* IEEE address for this node.
*/
do {
/*
* In case no valid IEEE address is available, a random
* IEEE address will be generated to be able to run the
* applications for demonstration purposes.
* In production code this can be omitted.
*/
/*
* The proper seed for function rand() has already been
*generated
* in function tal_generate_rand_seed().
*/
uint8_t *ptr_pib = (uint8_t *)&tal_pib.IeeeAddress;
for (uint8_t i = 0; i < 8; i++) {
*ptr_pib++ = (uint8_t)rand();
/*
* Note:
* Even if casting the 16 bit rand value back to
*8 bit,
* and running the loop 8 timers (instead of
*only 4 times)
* may look cumbersome, it turns out that the
*code gets
* smaller using 8-bit here.
* And timing is not an issue at this place...
*/
}
}
/* Check if a valid IEEE address is available. */
while ((tal_pib.IeeeAddress == 0x0000000000000000) ||
(tal_pib.IeeeAddress == 0xFFFFFFFFFFFFFFFF)
);
} else {
/* Valid IEEE address, so no need to generate a new random seed.
**/
uint16_t cur_rand_seed = (uint16_t)tal_pib.IeeeAddress;
srand(cur_rand_seed);
}
#else
/*
* No check for a valid IEEE address done, so directly create a seed
* for srand().
*/
tal_generate_rand_seed();
#endif
/*
* Do the reset stuff.
* Set the default PIBs.
*/
if (internal_tal_reset(true) != MAC_SUCCESS) {
return FAILURE;
}
pal_trx_reg_read(RG_IRQ_STATUS); /* clear pending irqs, dummy read */
/*
* Configure interrupt handling.
* Install a handler for the transceiver interrupt.
*/
pal_trx_irq_init((FUNC_PTR)trx_irq_handler_cb);
pal_trx_irq_en(); /* Enable transceiver main interrupt. */
/* Initialize the buffer management module and get a buffer to store
*reveived frames. */
bmm_buffer_init();
tal_rx_buffer = bmm_buffer_alloc(LARGE_BUFFER_SIZE);
/* Init incoming frame queue */
#ifdef ENABLE_QUEUE_CAPACITY
qmm_queue_init(&tal_incoming_frame_queue,
TAL_INCOMING_FRAME_QUEUE_CAPACITY);
#else
qmm_queue_init(&tal_incoming_frame_queue);
#endif /* ENABLE_QUEUE_CAPACITY */
return MAC_SUCCESS;
} /* tal_init() */
