0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps8, 1050, 1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps8_config2, 1050, 1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps9, 2800, 2800, tps65090_rails(DCDC2), 1, 0, 0, NORMAL, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo1, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo1_config2, 1200, 1200, tps65090_rails(DCDC2), 0, 0, 1, 0, 1, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo2, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo2_config2, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo3, 1200, 1200, palmas_rails(smps3), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo4_config2, 1200, 1200, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo4, 1800, 1800, tps65090_rails(DCDC2), 0, 0, 0, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo6, 2850, 2850, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo7, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo8, 900, 900, tps65090_rails(DCDC3), 1, 1, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo9, 1800, 3300, palmas_rails(smps9), 0, 0, 1, 0, 1, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, 0, 0, 0, 0, 0);
.gpio = _gpio_nr, \
.gpio_is_open_drain = _open_drain, \
.enable_high = _active_high, \
.enabled_at_boot = _boot_state, \
.init_data = &ri_data_##_var, \
}; \
static struct platform_device fixed_reg_##_var##_dev = { \
.name = "reg-fixed-voltage", \
.id = _id, \
.dev = { \
.platform_data = &fixed_reg_##_var##_pdata, \
}, \
}
FIXED_REG(0, fan_5v0, fan_5v0,
palmas_rails(smps10), 0, 0,
PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 5000);
FIXED_REG(1, vdd_hdmi_5v0, vdd_hdmi_5v0,
palmas_rails(smps10), 0, 0,
TEGRA_GPIO_PK1, false, true, 0, 5000);
FIXED_REG(2, lcd_bl_en, lcd_bl_en,
NULL, 0, 0,
TEGRA_GPIO_PH2, false, true, 1, 5000);
FIXED_REG(3, avdd_ts, avdd_ts,
palmas_rails(regen1), 0, 0,
TEGRA_GPIO_PH5, false, true, 0, 3300);
FIXED_REG(4, dvdd_ts, dvdd_ts,
PALMAS_REGS_PDATA(smps123, 900, 1350, NULL, 0, 0, 0, 0, 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 3, 0); PALMAS_REGS_PDATA(smps45, 900, 1400, NULL, 0, 0, 0, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps6, 3200, 3200, NULL, 0, 0, 1, NORMAL, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps7, 1350, 1350, NULL, 0, 0, 1, NORMAL, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps9, 2900, 2900, NULL, 1, 0, 1, NORMAL, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps10, 5000, 5000, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo1, 1050, 1050, palmas_rails(smps7), 1, 0, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(ldo2, 1200, 1200, palmas_rails(smps7), 0, 1, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo3, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo5, 2800, 2800, palmas_rails(smps9), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo6, 2850, 2850, palmas_rails(smps9), 0, 1, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo8, 950, 950, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
int __init atlantis_regulator_init(void)
{
struct board_info board_info;
void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
u32 pmc_ctrl;
int i;
bool wdt_disable;
/* configure the power management controller to trigger PMU
* interrupts when high */
pmc_ctrl = readl(pmc + PMC_CTRL);
writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
tegra_get_board_info(&board_info);
for (i = 0; i < PALMAS_NUM_REGS ; i++) {
pmic_platform.reg_data[i] = atlantis_reg_data[i];
pmic_platform.reg_init[i] = atlantis_reg_init[i];
}
reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS6;
/* Enable full constraints to disable unused rails */
regulator_has_full_constraints();
/* Set LDO11 startup time to 600us */
reg_idata_ldo11.constraints.startup_delay = 600;
if (((board_info.fab != BOARD_FAB_A00) ||
(board_info.board_id == BOARD_E1740)))
reg_idata_regen7.num_consumer_supplies = 0;
if (board_info.sku == BOARD_SKU_110) {
pmic_platform.reg_data[PALMAS_REG_SMPS12] = NULL;
pmic_platform.reg_init[PALMAS_REG_SMPS12] = NULL;
lp8755_regulator_init();
} else if (board_info.sku == BOARD_SKU_100 ||
board_info.board_id == BOARD_E1740) {
reg_init_data_smps12.roof_floor = PALMAS_EXT_CONTROL_ENABLE1;
} else if (board_info.sku == BOARD_SKU_120) {
pmic_platform.reg_data[PALMAS_REG_SMPS12] =
atlantis_reg_data[PALMAS_REG_SMPS6];
pmic_platform.reg_data[PALMAS_REG_SMPS12]->constraints.name =
palmas_rails(smps12);
pmic_platform.reg_init[PALMAS_REG_SMPS12] =
atlantis_reg_init[PALMAS_REG_SMPS6];
pmic_platform.reg_data[PALMAS_REG_SMPS6] = NULL;
pmic_platform.reg_init[PALMAS_REG_SMPS6] = NULL;
reg_init_data_ldo5.config_flags =
PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE;
reg_init_data_ldo5.tracking_regulator = PALMAS_REG_SMPS12;
lp8755_regulator_init();
}
platform_device_register(&power_supply_extcon_device);
if (board_info.board_id == BOARD_E1670) {
gadc_thermal_battery_pdata.adc_temp_lookup =
atlanties_ers_batt_temperature_table;
gadc_thermal_battery_pdata.lookup_table_size =
ARRAY_SIZE(atlanties_ers_batt_temperature_table);
gadc_thermal_battery_pdata.first_index_temp = 119;
gadc_thermal_battery_pdata.last_index_temp = -40;
} else if (board_info.board_id == BOARD_E1740) {
gadc_thermal_battery_pdata.adc_temp_lookup = atlantis_ffd_batt_temperature_table;
gadc_thermal_battery_pdata.lookup_table_size = ARRAY_SIZE(atlantis_ffd_batt_temperature_table);
gadc_thermal_battery_pdata.first_index_temp = 125;
gadc_thermal_battery_pdata.last_index_temp = -40;
}
if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) {
palmas_pdata.battery_pdata->is_battery_present = true;
palmas_pdata.charger_pdata->bcharger_pdata =
&palmas_bcharger_pdata;
platform_device_register(&gadc_thermal_battery);
}
wdt_disable = is_pmic_wdt_disabled_at_boot();
if (wdt_disable)
palmas_pdata.watchdog_timer_initial_period = 0;
i2c_register_board_info(4, palma_device,
ARRAY_SIZE(palma_device));
return 0;
}
PALMAS_REGS_PDATA(smps12, 650, 1300, NULL, 0, 0, 0, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps3, 1100, 1100, NULL, 0, 0, 0, 0, 0, PALMAS_EXT_CONTROL_ENABLE2, 0, 10000, 0); PALMAS_REGS_PDATA(smps6, 650, 1400, NULL, 0, 0, 0, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(smps7, 2840, 2860, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps8, 1200, 1200, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(smps9, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo1, 3200, 3200, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo2, 2850, 2850, palmas_rails(smps7), 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo3, 1800, 3000, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo4, 1050, 1050, palmas_rails(smps8), 1, 0, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); PALMAS_REGS_PDATA(ldo5, 800, 800, palmas_rails(smps8), 1, 0, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 1, 0, 0); PALMAS_REGS_PDATA(ldo6, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo7, 1800, 3000, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo8, 1800, 1800, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0); PALMAS_REGS_PDATA(ldo9, 900, 1100, palmas_rails(smps8), 0, 0, 1, 0, 0, 0, 0, 0, 0);
REGULATOR_SUPPLY("vdd", "1-004c"),
REGULATOR_SUPPLY("vdd", "1-004d"),
REGULATOR_SUPPLY("vcc", "1-0071"),
};
PALMAS_REGS_PDATA(ti913_smps123, 650, 1400, NULL, 0, 1, 1, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps45, 700, 1400, NULL, 1, 1, 1, NORMAL,
0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps6, 1800, 1800, NULL, 1, 1, 1, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps7, 900, 1350, NULL, 1, 1, 1, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_smps9, 1050, 1050, NULL, 0, 0, 0, NORMAL,
0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo1, 1050, 1250, palmas_rails(ti913_smps7),
1, 1, 1, 0, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo2, 1200, 1200, palmas_rails(ti913_smps6),
0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo3, 3100, 3100, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo4, 1200, 1200, palmas_rails(ti913_smps6),
0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo5, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo6, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo7, 2700, 2700, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo8, 800, 800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldo9, 1800, 3300, NULL, 0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldoln, 1050, 1050, palmas_rails(ti913_smps6),
0, 0, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_ldousb, 1800, 1800, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
PALMAS_REGS_PDATA(ti913_regen1, 2800, 3300, NULL, 1, 1, 1, 0, 0, 0, 0, 0, 0);
.gpio = _gpio_nr, \
.gpio_is_open_drain = _open_drain, \
.enable_high = _active_high, \
.enabled_at_boot = _boot_state, \
.init_data = &ri_data_##_var, \
}; \
static struct platform_device fixed_reg_##_var##_dev = { \
.name = "reg-fixed-voltage", \
.id = _id, \
.dev = { \
.platform_data = &fixed_reg_##_var##_pdata, \
}, \
}
FIXED_REG(0, fan_5v0, fan_5v0,
palmas_rails(smps10_out2), 0, 0,
PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 5000);
FIXED_REG(1, vdd_hdmi_5v0, vdd_hdmi_5v0,
palmas_rails(smps10_out2), 0, 0,
TEGRA_GPIO_PK1, false, true, 0, 5000);
FIXED_REG(2, lcd_bl_en, lcd_bl_en,
NULL, 0, 0,
TEGRA_GPIO_PH2, false, true, 1, 5000);
FIXED_REG(3, avdd_ts, avdd_ts,
palmas_rails(regen1), 0, 0,
TEGRA_GPIO_PH5, false, true, 0, 3300);
FIXED_REG(4, dvdd_ts, dvdd_ts,
REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"),
REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"),
REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"),
REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"),
REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"),
};
PALMAS_PDATA_INIT(smps12, 1350, 1350, tps65090_rails(DCDC3), 0, 0, 0, NORMAL, 0);
PALMAS_PDATA_INIT(smps3, 1800, 1800, tps65090_rails(DCDC3), 0, 0, 0, NORMAL, 0);
PALMAS_PDATA_INIT(smps45, 900, 1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL, 0);
PALMAS_PDATA_INIT(smps457, 900, 1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL, 0);
PALMAS_PDATA_INIT(smps8, 1050, 1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL, 0);
PALMAS_PDATA_INIT(smps9, 2800, 2800, tps65090_rails(DCDC2), 1, 0, 0, NORMAL, 0);
PALMAS_PDATA_INIT(ldo1, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldo2, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldo3, 1200, 1200, palmas_rails(smps3), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldo4, 1800, 1800, tps65090_rails(DCDC2), 0, 0, 0, 0, 0);
PALMAS_PDATA_INIT(ldo6, 2850, 2850, tps65090_rails(DCDC2), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldo7, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldo8, 900, 900, tps65090_rails(DCDC3), 1, 1, 1, 0, 0);
PALMAS_PDATA_INIT(ldo9, 1800, 3300, palmas_rails(smps9), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, 0);
PALMAS_PDATA_INIT(ldousb, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, 0);
#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname
static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = {
PALMAS_REG_PDATA(smps12),
NULL,
PALMAS_REG_PDATA(smps3),
PALMAS_REG_PDATA(smps45),
