// -------------------------------------------------------
VHDL_File_Info::VHDL_File_Info(QString File, bool isfile)
{
if (isfile) {
QFile f(File);
if(!f.open(QIODevice::ReadOnly))
File = "";
else {
QByteArray FileContent = f.readAll();
File = QString(FileContent);
}
f.close();
}
QString s;
PortNames = "";
int i=0, j, k=0;
while((i=File.indexOf("--", i)) >= 0) { // remove all VHDL comments
j = File.indexOf('\n', i+2); // This also finds "--" within a ...
if(j < 0) // string, but as no strings are ...
File = File.left(i); // allowed in entity headers, it ...
else // does not matter.
File.remove(i, j-i);
}
QRegExp Expr;
Expr.setCaseSensitivity(Qt::CaseInsensitive);
for(;;) {
k--;
Expr.setPattern("\\bentity\\b"); // start of last entity
k = File.lastIndexOf(Expr, k);
if(k < 0)
return;
Expr.setPattern("\\bend\\b"); // end of last entity
i = File.indexOf(Expr, k+7);
if(i < 0)
return;
s = File.mid(k+7, i-k-7); // cut out entity declaration
Expr.setPattern("\\b");
i = s.indexOf(Expr);
if(i < 0)
return;
j = s.indexOf(Expr, i+1);
if(j < 0)
return;
EntityName = s.mid(i, j-i); // save entity name
i = s.indexOf(Expr, j+1);
if(i < 0)
return;
j = s.indexOf(Expr, i+1);
if(j < 0)
return;
if(s.mid(i, j-i).toLower() == "is") // really found start of entity ?
break;
if(k < 1) // already searched the whole text
return;
}
// parse ports, i.e. network connections; and generics, i.e. parameters
GenNames = parseGenerics(s,j);
PortNames = parsePorts(s,j);
}
// -------------------------------------------------------
Verilog_File_Info::Verilog_File_Info(QString File, bool isfile)
{
if (isfile) {
QFile f(File);
if(!f.open(QIODevice::ReadOnly))
File = "";
else {
QByteArray FileContent = f.readAll();
File = QString(FileContent);
}
f.close();
}
QString s;
int i=0, j, k=0;
while((i=File.find("//", i)) >= 0) { // remove all Verilog comments
j = File.find('\n', i+2); // (This also finds "//" within a ...
if(j < 0) // string, but as no strings are ...
File = File.left(i); // allowed in module headers, it ...
else // does not matter.)
File.remove(i, j-i);
}
i=0;
while((i=File.find("/*", i)) >= 0) { // remove all Verilog comments
j = File.find("*/", i+2); // (This also finds "/*" within a ...
if(j < 0) // string, but as no strings are ...
File = File.left(i); // allowed in module headers, it ...
else // does not matter.)
File.remove(i, j-i+2);
}
QRegExp Expr,Expr1;
Expr.setCaseSensitive(true);
Expr1.setCaseSensitive(true);
k--;
Expr.setPattern("\\bmodule\\b"); // start of last module
k = File.findRev(Expr, k);
if(k < 0)
return;
Expr.setPattern("\\bendmodule\\b"); // end of last module
i = File.find(Expr, k+7);
if(i < 0)
return;
s = File.mid(k+7, i-k-7); // cut out module declaration
Expr.setPattern("\\b");
i = s.find(Expr);
if(i < 0)
return;
j = s.find(Expr, i+1);
if(j < 0)
return;
ModuleName = s.mid(i, j-i); // save module name
i = s.find('(', j);
if(i < 0)
return;
j = s.find(')', i);
if(j < 0)
return;
s = s.mid(i+1, j-i-1);
// parse ports, i.e. network connections; and generics, i.e. parameters
PortNames = parsePorts (s, 0);
}
