void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
struct device *dev = NB_DEV_ROOT;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
/* Parse device tree and disable unused device*/
parse_devicetree(silconfig);
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0)
silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
if (cfg->emmc_tx_data_cntl2 != 0)
silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
if (cfg->emmc_rx_cmd_data_cntl1 != 0)
silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
if (cfg->emmc_rx_strobe_cntl != 0)
silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
silconfig->MonitorMwaitEnable = 0;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
/* Disable FSP from locking access to the RTC NVRAM */
silconfig->RtcLock = 0;
/* Enable Audio clk gate and power gate */
silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
}
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
{
struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
struct device *dev = NB_DEV_ROOT;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
/* Parse device tree and disable unused device*/
parse_devicetree(silconfig);
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
if (cfg->emmc_tx_data_cntl1 != 0)
silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
if (cfg->emmc_tx_data_cntl2 != 0)
silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
if (cfg->emmc_rx_cmd_data_cntl1 != 0)
silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
if (cfg->emmc_rx_strobe_cntl != 0)
silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
}
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
/* Parse device tree and enable/disable devices */
parse_devicetree(params);
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
params->Usb3OverCurrentPin[i] = 0;
}
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
if (config->psys_pmax) {
printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax);
/* PsysPmax is in unit of 1/8 Watt */
tconfig->PsysPmax = config->psys_pmax * 8;
}
/* Unlock upper 8 bytes of RTC RAM */
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
dev = dev_find_slot(0, PCH_DEVFN_SATA);
if (!dev)
params->SataEnable = 0;
else {
params->SataEnable = dev->enabled;
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
}
/* Lan */
dev = dev_find_slot(0, PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else {
params->PchLanEnable = dev->enabled;
if (config->s0ix_enable) {
params->SlpS0WithGbeSupport = 1;
params->PchPmSlpS0VmRuntimeControl = 0;
params->PchPmSlpS0Vm070VSupport = 0;
params->PchPmSlpS0Vm075VSupport = 0;
ignore_gbe_ltr();
}
}
/* Audio */
params->PchHdaDspEnable = config->PchHdaDspEnable;
params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
/* eDP device */
params->DdiPortEdp = config->DdiPortEdp;
/* HPD of DDI ports */
params->DdiPortBHpd = config->DdiPortBHpd;
params->DdiPortCHpd = config->DdiPortCHpd;
params->DdiPortDHpd = config->DdiPortDHpd;
params->DdiPortFHpd = config->DdiPortFHpd;
/* DDC of DDI ports */
params->DdiPortBDdc = config->DdiPortBDdc;
params->DdiPortCDdc = config->DdiPortCDdc;
params->DdiPortDDdc = config->DdiPortDDdc;
params->DdiPortFDdc = config->DdiPortFDdc;
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =
config->usb3_ports[i].tx_de_emp;
}
if (config->usb3_ports[i].tx_downscale_amp) {
params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
params->Usb3HsioTxDownscaleAmp[i] =
config->usb3_ports[i].tx_downscale_amp;
}
}
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
/* Enable CNVi Wifi if enabled in device tree */
dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE)
params->CnviMode = dev->enabled;
#else
params->PchCnviMode = dev->enabled;
#endif
/* PCI Express */
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
if (config->PcieClkSrcUsage[i] == 0)
config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
}
memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(config->PcieRpHotPlug));
/* eMMC and SD */
dev = dev_find_slot(0, PCH_DEVFN_EMMC);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
params->ScsEmmcEnabled = dev->enabled;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->PchScsEmmcHs400DllDataValid = config->EmmcHs400DllNeed;
if (config->EmmcHs400DllNeed == 1) {
params->PchScsEmmcHs400RxStrobeDll1 =
config->EmmcHs400RxStrobeDll1;
params->PchScsEmmcHs400TxDataDll =
config->EmmcHs400TxDataDll;
}
}
dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
if (!dev) {
params->ScsSdCardEnabled = 0;
} else {
params->ScsSdCardEnabled = dev->enabled;
params->SdCardPowerEnableActiveHigh =
CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
}
dev = dev_find_slot(0, PCH_DEVFN_UFS);
if (!dev)
params->ScsUfsEnabled = 0;
else
params->ScsUfsEnabled = dev->enabled;
params->Heci3Enabled = config->Heci3Enabled;
params->Device4Enable = config->Device4Enable;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Acoustic Noise Mitigation */
params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
params->SlowSlewRateForIa = config->SlowSlewRateForIa;
params->SlowSlewRateForGt = config->SlowSlewRateForGt;
params->SlowSlewRateForSa = config->SlowSlewRateForSa;
params->SlowSlewRateForFivr = config->SlowSlewRateForFivr;
params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa;
params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Power Optimizer */
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
if (config->PchPmSlpS4MinAssert)
params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
if (config->PchPmSlpSusMinAssert)
params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
if (config->PchPmSlpAMinAssert)
params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
/* Unlock all GPIO pads */
tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;
}
