static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* PME */ if(ps->gpe0_sts[GPE0_A] & CSE_PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); /* ACPI Wake Event - Always Log prev_sleep_state*/ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); /* Log GPIO events in set A-D */ pch_log_gpio_gpe(ps->gpe0_sts[GPE0_A], ps->gpe0_en[GPE0_A], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_B], ps->gpe0_en[GPE0_B], 32); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_C], ps->gpe0_en[GPE0_C], 64); pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96); }
static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); /* Internal PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); /* GPIO27 */ if (ps->gpe0_sts[GPE_STD] & GP27_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); }
static void pch_lp_log_gpe(void) { /* Standard GPE are in GPE set 4 */ pch_log_standard_gpe(LP_GPE0_STS_4, LP_GPE0_EN_4); /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(LP_GPE0_STS_1, LP_GPE0_EN_1, 0); pch_log_gpio_gpe(LP_GPE0_STS_2, LP_GPE0_EN_2, 32); pch_log_gpio_gpe(LP_GPE0_STS_3, LP_GPE0_EN_3, 64); }