static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, struct list_head *resources) { struct resource *res; unsigned long io_offset; int i; io_offset = (unsigned long)pci_ctrl->io_space.base; res = &pci_ctrl->io_resource; if (!res->flags) { if (io_offset) printk (KERN_ERR "I/O resource not set for host" " bridge %d\n", pci_ctrl->index); res->start = 0; res->end = IO_SPACE_LIMIT; res->flags = IORESOURCE_IO; } res->start += io_offset; res->end += io_offset; pci_add_resource(resources, res); for (i = 0; i < 3; i++) { res = &pci_ctrl->mem_resources[i]; if (!res->flags) { if (i > 0) continue; printk(KERN_ERR "Memory resource not set for " "host bridge %d\n", pci_ctrl->index); res->start = 0; res->end = ~0U; res->flags = IORESOURCE_MEM; } pci_add_resource(resources, res); } }
static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys) { if (nr > 0) return 0; request_resource(&iomem_resource, &pci_mem); request_resource(&ioport_resource, &pci_io); pci_add_resource(&sys->resources, &pci_io); pci_add_resource(&sys->resources, &pci_mem); /* Assign and enable processor bridge */ ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); /* Enable bus-master & Memory Space access */ ks8695_local_writeconfig(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Set cache-line size & latency. */ ks8695_local_writeconfig(PCI_CACHE_LINE_SIZE, (32 << 8) | (L1_CACHE_BYTES / sizeof(u32))); /* Reserve PCI memory space for PCI-AHB resources */ if (!request_mem_region(KS8695_PCIMEM_PA, SZ_64M, "PCI-AHB Bridge")) { printk(KERN_ERR "Cannot allocate PCI-AHB Bridge memory.\n"); return -EBUSY; } return 1; }
static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; if (nr >= num_pcie_ports) return 0; pp = &pcie_port[nr]; pp->root_bus_nr = sys->busnr; /* * Generic PCIe unit setup. */ orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); /* * IORESOURCE_IO */ snprintf(pp->io_space_name, sizeof(pp->io_space_name), "PCIe %d I/O", pp->index); pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; pp->res[0].name = pp->io_space_name; if (pp->index == 0) { pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; } else { pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; } pp->res[0].flags = IORESOURCE_IO; if (request_resource(&ioport_resource, &pp->res[0])) panic("Request PCIe IO resource failed\n"); pci_add_resource(&sys->resources, &pp->res[0]); /* * IORESOURCE_MEM */ snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; pp->res[1].name = pp->mem_space_name; if (pp->index == 0) { pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; } else { pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; } pp->res[1].flags = IORESOURCE_MEM; if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Memory resource failed\n"); pci_add_resource(&sys->resources, &pp->res[1]); return 1; }
static int __init pcie_setup(struct pci_sys_data *sys) { struct resource *res; int dev; /* * Generic PCIe unit setup. */ orion_pcie_setup(PCIE_BASE); /* * Check whether to apply Orion-1/Orion-NAS PCIe config * read transaction workaround. */ dev = orion_pcie_dev_id(PCIE_BASE); if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " "read transaction workaround\n"); orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, ORION5X_PCIE_WA_SIZE); pcie_ops.read = pcie_rd_conf_wa; } /* * Request resources. */ res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); if (!res) panic("pcie_setup unable to alloc resources"); /* * IORESOURCE_IO */ res[0].name = "PCIe I/O Space"; res[0].flags = IORESOURCE_IO; res[0].start = ORION5X_PCIE_IO_BUS_BASE; res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; if (request_resource(&ioport_resource, &res[0])) panic("Request PCIe IO resource failed\n"); pci_add_resource(&sys->resources, &res[0]); /* * IORESOURCE_MEM */ res[1].name = "PCIe Memory Space"; res[1].flags = IORESOURCE_MEM; res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; if (request_resource(&iomem_resource, &res[1])) panic("Request PCIe Memory resource failed\n"); pci_add_resource(&sys->resources, &res[1]); sys->io_offset = 0; return 1; }
int __init pci_mcs8140_setup_resources(struct pci_sys_data *sys) { int ret = 0; ret = request_resource(&iomem_resource, &io_mem); if (ret) { pr_err("PCI: unable to allocate I/O " "memory region (%d)\n", ret); goto out; } ret = request_resource(&iomem_resource, &non_mem); if (ret) { pr_err("PCI: unable to allocate non-prefetchable " "memory region (%d)\n", ret); goto release_io_mem; } ret = request_resource(&iomem_resource, &pre_mem); if (ret) { pr_err("PCI: unable to allocate prefetchable " "memory region (%d)\n", ret); goto release_non_mem; } mcs8140_eeprom_emu_init(); pci_add_resource(&sys->resources, &io_mem); pci_add_resource(&sys->resources, &non_mem); pci_add_resource(&sys->resources, &pre_mem); return ret; release_non_mem: release_resource(&non_mem); release_io_mem: release_resource(&io_mem); out: return ret; }
struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) { struct acpi_device *device = root->device; struct pci_root_info *info = NULL; int domain = root->segment; int busnum = root->secondary.start; LIST_HEAD(resources); struct pci_bus *bus = NULL; struct pci_sysdata *sd; int node; #ifdef CONFIG_ACPI_NUMA int pxm; #endif if (pci_ignore_seg) domain = 0; if (domain && !pci_domains_supported) { printk(KERN_WARNING "pci_bus %04x:%02x: " "ignored (multiple domains not supported)\n", domain, busnum); return NULL; } node = -1; #ifdef CONFIG_ACPI_NUMA pxm = acpi_get_pxm(device->handle); if (pxm >= 0) node = pxm_to_node(pxm); if (node != -1) set_mp_bus_to_node(busnum, node); else #endif node = get_mp_bus_to_node(busnum); if (node != -1 && !node_online(node)) node = -1; info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) { printk(KERN_WARNING "pci_bus %04x:%02x: " "ignored (out of memory)\n", domain, busnum); return NULL; } sd = &info->sd; sd->domain = domain; sd->node = node; sd->companion = device; /* * Maybe the desired pci bus has been already scanned. In such case * it is unnecessary to scan the pci bus with the given domain,busnum. */ bus = pci_find_bus(domain, busnum); if (bus) { /* * If the desired bus exits, the content of bus->sysdata will * be replaced by sd. */ memcpy(bus->sysdata, sd, sizeof(*sd)); kfree(info); } else { probe_pci_root_info(info, device, busnum, domain); /* insert busn res at first */ pci_add_resource(&resources, &root->secondary); /* * _CRS with no apertures is normal, so only fall back to * defaults or native bridge info if we're ignoring _CRS. */ if (pci_use_crs) add_resources(info, &resources); else { free_pci_root_info_res(info); x86_pci_root_bus_resources(busnum, &resources); } if (!setup_mcfg_map(info, domain, (u8)root->secondary.start, (u8)root->secondary.end, root->mcfg_addr)) bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); if (bus) { pci_scan_child_bus(bus); pci_set_host_bridge_release( to_pci_host_bridge(bus->bridge), release_pci_root_info, info); } else { pci_free_resource_list(&resources); __release_pci_root_info(info); } } /* After the PCI-E bus has been walked and all devices discovered, * configure any settings of the fabric that might be necessary. */ if (bus) { struct pci_bus *child; list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child); } if (bus && node != -1) { #ifdef CONFIG_ACPI_NUMA if (pxm >= 0) dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d (pxm %d)\n", node, pxm); #else dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node); #endif } return bus; }
void __init nautilus_init_pci(void) { struct pci_controller *hose = hose_head; struct pci_host_bridge *bridge; struct pci_bus *bus; struct pci_dev *irongate; unsigned long bus_align, bus_size, pci_mem; unsigned long memtop = max_low_pfn << PAGE_SHIFT; int ret; bridge = pci_alloc_host_bridge(0); if (!bridge) return; pci_add_resource(&bridge->windows, &ioport_resource); pci_add_resource(&bridge->windows, &iomem_resource); pci_add_resource(&bridge->windows, &busn_resource); bridge->dev.parent = NULL; bridge->sysdata = hose; bridge->busnr = 0; bridge->ops = alpha_mv.pci_ops; bridge->swizzle_irq = alpha_mv.pci_swizzle; bridge->map_irq = alpha_mv.pci_map_irq; /* Scan our single hose. */ ret = pci_scan_root_bus_bridge(bridge); if (ret) { pci_free_host_bridge(bridge); return; } bus = hose->bus = bridge->bus; pcibios_claim_one_bus(bus); irongate = pci_get_bus_and_slot(0, 0); bus->self = irongate; bus->resource[0] = &irongate_io; bus->resource[1] = &irongate_mem; pci_bus_size_bridges(bus); /* IO port range. */ bus->resource[0]->start = 0; bus->resource[0]->end = 0xffff; /* Set up PCI memory range - limit is hardwired to 0xffffffff, base must be at aligned to 16Mb. */ bus_align = bus->resource[1]->start; bus_size = bus->resource[1]->end + 1 - bus_align; if (bus_align < 0x1000000UL) bus_align = 0x1000000UL; pci_mem = (0x100000000UL - bus_size) & -bus_align; bus->resource[1]->start = pci_mem; bus->resource[1]->end = 0xffffffffUL; if (request_resource(&iomem_resource, bus->resource[1]) < 0) printk(KERN_ERR "Failed to request MEM on hose 0\n"); if (pci_mem < memtop) memtop = pci_mem; if (memtop > alpha_mv.min_mem_address) { free_reserved_area(__va(alpha_mv.min_mem_address), __va(memtop), -1, NULL); printk("nautilus_init_pci: %ldk freed\n", (memtop - alpha_mv.min_mem_address) >> 10); }