// Enable shadowing and copy bios.
static void
__make_bios_writable_intel(u16 bdf, u32 pam0)
{
// Make ram from 0xc0000-0xf0000 writable
int clear = 0;
int i;
for (i=0; i<6; i++) {
u32 pam = pam0 + 1 + i;
int reg = pci_config_readb(bdf, pam);
if (CONFIG_OPTIONROMS_DEPLOYED && (reg & 0x11) != 0x11) {
// Need to copy optionroms to work around qemu implementation
void *mem = (void*)(BUILD_ROM_START + i * 32*1024);
memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024);
pci_config_writeb(bdf, pam, 0x33);
memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024);
clear = 1;
} else {
pci_config_writeb(bdf, pam, 0x33);
}
}
if (clear)
memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
// Make ram from 0xf0000-0x100000 writable
int reg = pci_config_readb(bdf, pam0);
pci_config_writeb(bdf, pam0, 0x30);
if (reg & 0x10)
// Ram already present.
return;
// Copy bios.
extern u8 code32flat_start[], code32flat_end[];
memcpy(code32flat_start, code32flat_start + BIOS_SRC_OFFSET
, code32flat_end - code32flat_start);
}
int
pci_next(int bdf, int *pmax)
{
int max;
if (PCI_FUNC(bdf) == 1)
{
/* If the last device was not a multi-function device, skip to next. */
if ((pci_config_readb(bdf-1, PCI_HEADER_TYPE) & 0x80) == 0)
bdf += 7;
}
max = *pmax;
while (1)
{
uint16_t vendor;
/* ??? Support multiple PCI busses here at some point. */
if (bdf >= max)
return -1;
/* Check if there is a device present at the location. */
vendor = pci_config_readw(bdf, PCI_VENDOR_ID);
if (vendor != 0x0000 && vendor != 0xffff)
return bdf;
bdf += (PCI_FUNC(bdf) == 0 ? 8 : 1);
}
}
static int
getAMDRamSpeed(void)
{
struct pci_device *pci = pci_find_device(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL);
if (!pci)
return -1;
/* mem clk 0 = DDR2 400 */
return (pci_config_readb(pci->bdf, 0x94) & 0x7) + 6;
}
static int
getFBSize(struct pci_device *pci)
{
/* FB config */
u8 reg = pci_config_readb(pci->bdf, 0xa1);
/* GFX disabled ? */
if (!(reg & 0x80))
return -1;
static u8 mem_power[] = {0, 3, 4, 5, 6, 7, 8, 9};
return mem_power[(reg >> 4) & 0x7];
}
void
make_bios_writable_intel(u16 bdf, u32 pam0)
{
int reg = pci_config_readb(bdf, pam0);
if (!(reg & 0x10)) {
// QEMU doesn't fully implement the piix shadow capabilities -
// if ram isn't backing the bios segment when shadowing is
// disabled, the code itself wont be in memory. So, run the
// code from the high-memory flash location.
u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET;
void (*func)(u16 bdf, u32 pam0) = (void*)pos;
func(bdf, pam0);
return;
}
// Ram already present - just enable writes
__make_bios_writable_intel(bdf, pam0);
}
static int
getViaRamSpeed(struct pci_device *pci)
{
return (pci_config_readb(pci->bdf, 0x90) & 0x07) + 3;
}
