static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) { SHPCIC *pcic = p; switch(addr) { case 0 ... 0xfc: cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); break; case 0x1c0: pcic->par = val; break; case 0x1c4: pcic->mbr = val & 0xff000001; break; case 0x1c8: if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, IO_MEM_UNASSIGNED); pcic->iobr = val & 0xfffc0001; isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); } break; case 0x220: pci_data_write(pcic->bus, pcic->par, val, 4); break; } }
static void ppc_pci_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { PREPPCIState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size); }
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) { PREPPCIState *s = opaque; #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); }
static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN val = bswap32(val); #endif pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4); }
static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) { SHPCIC *pcic = p; switch(addr) { case 0 ... 0xfc: cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); break; case 0x1c0: pcic->par = val; break; case 0x1c4: pcic->mbr = val; break; case 0x1c8: pcic->iobr = val; break; case 0x220: pci_data_write(pcic->bus, pcic->par, val, 4); break; } }
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) { PREPPCIState *s = opaque; pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); }
static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) { pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1); }
static void bw_conf1_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { PCIBus *b = opaque; pci_data_write(b, addr, val, size); }
static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr, uint64_t val, unsigned size) { pci_data_write(opaque, vpb_pci_config_addr(addr), val, size); }
static void dino_config_data_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { PCIHostState *s = opaque; pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); }
static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr, uint32_t val, int size) { pci_data_write(pcic->bus, addr + pcic->mbr, val, size); }
static void bw_conf1_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { PCIBus *b = opaque; pci_data_write(b, addr, val, size); }