/*
* Setup the architecture
*/
void __init corenet_ds_setup_arch(void)
{
mpc85xx_smp_init();
#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
pci_devs_phb_init();
#endif
fsl_pci_assign_primary();
swiotlb_detect_4g();
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
}
void __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
struct device_node *root = of_find_node_by_path("/");
for_each_child_of_node(root, node) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
isa_bridge_find_early(phb);
}
of_node_put(root);
pci_devs_phb_init();
/* Create EEH devices for all PHBs */
eeh_dev_phb_init();
/*
* PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = of_get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop) {
if (*prop)
pci_add_flags(PCI_PROBE_ONLY);
else
pci_clear_flags(PCI_PROBE_ONLY);
}
#ifdef CONFIG_PPC32 /* Will be made generic soon */
prop = of_get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop && *prop)
pci_add_flags(PCI_REASSIGN_ALL_BUS);
#endif /* CONFIG_PPC32 */
}
}
unsigned long __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
unsigned int index;
struct device_node *root = of_find_node_by_path("/");
index = 0;
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
pci_setup_phb_io(phb, index == 0);
index++;
}
of_node_put(root);
pci_devs_phb_init();
/*
* pci_probe_only and pci_assign_all_buses can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop)
pci_probe_only = *prop;
prop = get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop)
pci_assign_all_buses = *prop;
}
return 0;
}
void __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
struct device_node *root = of_find_node_by_path("/");
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
isa_bridge_find_early(phb);
}
of_node_put(root);
pci_devs_phb_init();
/*
* pci_probe_only and pci_assign_all_buses can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = of_get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop)
pci_probe_only = *prop;
#ifdef CONFIG_PPC32 /* Will be made generic soon */
prop = of_get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop && *prop)
ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
#endif /* CONFIG_PPC32 */
}
}
static void __init cell_find_and_init_phbs(void)
{
struct device_node *axon, *plb5, *plb4, *np;
int index = 0;
/* Old blades, use generic code */
axon = of_find_node_by_name(NULL, "axon");
if (axon == NULL) {
find_and_init_phbs();
return;
}
/* New blades, manually instanciate bridges for now as
* RHEL5 doesn't have the infrastructure to do it from
* of_platform
*/
for (; axon; axon = of_find_node_by_name(axon, "axon")) {
for (plb5 = NULL; !!(plb5 = of_get_next_child(axon, plb5));)
if (strcmp(plb5->name, "plb5") == 0)
break;
if (plb5 == NULL)
continue;
for (np = NULL; !!(np = of_get_next_child(plb5, np));)
if ((strcmp(np->name, "pcie") == 0) ||
(strcmp(np->name, "pciex") == 0))
cell_add_phb(np, index++);
for (plb4 = NULL; !!(plb4 = of_get_next_child(plb5, plb4));)
if (strcmp(plb4->name, "plb4") == 0)
break;
of_node_put(plb5);
if (plb4 == NULL)
continue;
for (np = NULL; !!(np = of_get_next_child(plb4, np));)
if (strcmp(np->name, "pcix") == 0)
cell_add_phb(np, index++);
of_node_put(plb4);
}
pci_devs_phb_init();
}
/******************************************************************
* Find all PHBs in the system and initialize a set of data
* structures to represent them.
******************************************************************/
unsigned long __init
find_and_init_phbs(void)
{
struct device_node *Pci_Node;
struct pci_controller *phb;
unsigned int root_addr_size_words = 0, this_addr_size_words = 0;
unsigned int this_addr_count = 0, range_stride;
unsigned int *ui_ptr = NULL, *ranges;
char *model;
struct pci_range64 range;
struct resource *res;
unsigned int memno, rlen, i, index;
unsigned int *opprop;
int has_isa = 0;
PPCDBG(PPCDBG_PHBINIT, "find_and_init_phbs\n");
read_pci_config = rtas_token("read-pci-config");
write_pci_config = rtas_token("write-pci-config");
ibm_read_pci_config = rtas_token("ibm,read-pci-config");
ibm_write_pci_config = rtas_token("ibm,write-pci-config");
if (naca->interrupt_controller == IC_OPEN_PIC) {
opprop = (unsigned int *)get_property(find_path_device("/"),
"platform-open-pic", NULL);
}
/* Get the root address word size. */
ui_ptr = (unsigned int *) get_property(find_path_device("/"),
"#size-cells", NULL);
if (ui_ptr) {
root_addr_size_words = *ui_ptr;
} else {
PPCDBG(PPCDBG_PHBINIT, "\tget #size-cells failed.\n");
return(-1);
}
if (find_type_devices("isa")) {
has_isa = 1;
PPCDBG(PPCDBG_PHBINIT, "\tFound an ISA bus.\n");
}
index = 0;
/******************************************************************
* Find all PHB devices and create an object for them.
******************************************************************/
for (Pci_Node = find_devices("pci"); Pci_Node != NULL; Pci_Node = Pci_Node->next) {
model = (char *) get_property(Pci_Node, "model", NULL);
if (model != NULL) {
phb = alloc_phb(Pci_Node, model, root_addr_size_words);
if (phb == NULL) return(-1);
}
else {
continue;
}
/* Get this node's address word size. */
ui_ptr = (unsigned int *) get_property(Pci_Node, "#size-cells", NULL);
if (ui_ptr)
this_addr_size_words = *ui_ptr;
else
this_addr_size_words = 1;
/* Get this node's address word count. */
ui_ptr = (unsigned int *) get_property(Pci_Node, "#address-cells", NULL);
if (ui_ptr)
this_addr_count = *ui_ptr;
else
this_addr_count = 3;
range_stride = this_addr_count + root_addr_size_words + this_addr_size_words;
memno = 0;
phb->io_base_phys = 0;
ranges = (unsigned int *) get_property(Pci_Node, "ranges", &rlen);
PPCDBG(PPCDBG_PHBINIT, "\trange_stride = 0x%lx, rlen = 0x%x\n", range_stride, rlen);
for (i = 0; i < (rlen/sizeof(*ranges)); i+=range_stride) {
/* Put the PCI addr part of the current element into a
* '64' struct.
*/
range = *((struct pci_range64 *)(ranges + i));
/* If this is a '32' element, map into a 64 struct. */
if ((range_stride * sizeof(int)) ==
sizeof(struct pci_range32)) {
range.parent_addr =
(unsigned long)(*(ranges + i + 3));
range.size =
(((unsigned long)(*(ranges + i + 4)))<<32) |
(*(ranges + i + 5));
} else {
range.parent_addr =
(((unsigned long)(*(ranges + i + 3)))<<32) |
(*(ranges + i + 4));
range.size =
(((unsigned long)(*(ranges + i + 5)))<<32) |
(*(ranges + i + 6));
}
PPCDBG(PPCDBG_PHBINIT, "\trange.parent_addr = 0x%lx\n",
range.parent_addr);
PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.hi = 0x%lx\n",
range.child_addr.a_hi);
PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.mid = 0x%lx\n",
range.child_addr.a_mid);
PPCDBG(PPCDBG_PHBINIT, "\trange.child_addr.lo = 0x%lx\n",
range.child_addr.a_lo);
PPCDBG(PPCDBG_PHBINIT, "\trange.size = 0x%lx\n",
range.size);
res = NULL;
switch ((range.child_addr.a_hi >> 24) & 0x3) {
case 1: /* I/O space */
PPCDBG(PPCDBG_PHBINIT, "\tIO Space\n");
phb->io_base_phys = range.parent_addr;
res = &phb->io_resource;
res->name = Pci_Node->full_name;
res->flags = IORESOURCE_IO;
phb->io_base_virt = __ioremap(phb->io_base_phys, range.size, _PAGE_NO_CACHE);
if (!pci_io_base) {
pci_io_base = (unsigned long)phb->io_base_virt;
if (has_isa)
isa_io_base = pci_io_base;
}
res->start = ((((unsigned long) range.child_addr.a_mid) << 32) | (range.child_addr.a_lo));
res->start += (unsigned long)phb->io_base_virt - pci_io_base;
res->end = res->start + range.size - 1;
res->parent = NULL;
res->sibling = NULL;
res->child = NULL;
phb->pci_io_offset = range.parent_addr -
((((unsigned long)
range.child_addr.a_mid) << 32) |
(range.child_addr.a_lo));
PPCDBG(PPCDBG_PHBINIT, "\tpci_io_offset = 0x%lx\n",
phb->pci_io_offset);
break;
case 2: /* mem space */
PPCDBG(PPCDBG_PHBINIT, "\tMem Space\n");
phb->pci_mem_offset = range.parent_addr -
((((unsigned long)
range.child_addr.a_mid) << 32) |
(range.child_addr.a_lo));
PPCDBG(PPCDBG_PHBINIT, "\tpci_mem_offset = 0x%lx\n",
phb->pci_mem_offset);
if (memno < sizeof(phb->mem_resources)/sizeof(phb->mem_resources[0])) {
res = &(phb->mem_resources[memno]);
++memno;
res->name = Pci_Node->full_name;
res->flags = IORESOURCE_MEM;
res->start = range.parent_addr;
res->end = range.parent_addr + range.size - 1;
res->parent = NULL;
res->sibling = NULL;
res->child = NULL;
}
break;
}
}
PPCDBG(PPCDBG_PHBINIT, "\tphb->io_base_phys = 0x%lx\n",
phb->io_base_phys);
PPCDBG(PPCDBG_PHBINIT, "\tphb->pci_mem_offset = 0x%lx\n",
phb->pci_mem_offset);
if (naca->interrupt_controller == IC_OPEN_PIC) {
int addr = root_addr_size_words * (index + 2) - 1;
openpic_setup_ISU(index, opprop[addr]);
}
index++;
}
pci_devs_phb_init();
return 0; /*Success */
}
unsigned long __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
unsigned int root_size_cells = 0;
unsigned int index;
unsigned int *opprop = NULL;
struct device_node *root = of_find_node_by_path("/");
if (ppc64_interrupt_controller == IC_OPEN_PIC) {
opprop = (unsigned int *)get_property(root,
"platform-open-pic", NULL);
}
root_size_cells = prom_n_size_cells(root);
index = 0;
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
if (node->type == NULL || strcmp(node->type, "pci") != 0)
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
setup_phb(node, phb, root_size_cells);
pci_process_bridge_OF_ranges(phb, node, 0);
pci_setup_phb_io(phb, index == 0);
#ifdef CONFIG_PPC_PSERIES
if (ppc64_interrupt_controller == IC_OPEN_PIC && pSeries_mpic) {
int addr = root_size_cells * (index + 2) - 1;
mpic_assign_isu(pSeries_mpic, index, opprop[addr]);
}
#endif
index++;
}
of_node_put(root);
pci_devs_phb_init();
/*
* pci_probe_only and pci_assign_all_buses can be set via properties
* in chosen.
*/
if (of_chosen) {
int *prop;
prop = (int *)get_property(of_chosen, "linux,pci-probe-only",
NULL);
if (prop)
pci_probe_only = *prop;
prop = (int *)get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop)
pci_assign_all_buses = *prop;
}
return 0;
}