static int
ofw_pcibus_assign_interrupt(device_t dev, device_t child)
{
ofw_pci_intr_t intr;
phandle_t node;
int isz;
node = ofw_bus_get_node(child);
if (node == -1) {
/* Non-firmware enumerated child, use standard routing */
/*
* XXX: Right now we don't have anything sensible to do here,
* since the ofw_imap stuff relies on nodes have a reg
* property. There exists ways around this, so the ePAPR
* spec will need to be studied.
*/
return (0);
#ifdef NOTYET
intr = pci_get_intpin(child);
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
intr));
#endif
}
/*
* Any AAPL,interrupts property gets priority and is
* fully specified (i.e. does not need routing)
*/
isz = OF_getprop(node, "AAPL,interrupts", &intr, sizeof(intr));
if (isz == sizeof(intr)) {
return (intr);
}
isz = OF_getprop(node, "interrupts", &intr, sizeof(intr));
if (isz != sizeof(intr)) {
/* No property; our best guess is the intpin. */
intr = pci_get_intpin(child);
}
/*
* If we got intr from a property, it may or may not be an intpin.
* For on-board devices, it frequently is not, and is completely out
* of the valid intpin range. For PCI slots, it hopefully is,
* otherwise we will have trouble interfacing with non-OFW buses
* such as cardbus.
* Since we cannot tell which it is without violating layering, we
* will always use the route_interrupt method, and treat exceptions
* on the level they become apparent.
*/
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
}
static int
ofw_pcibus_assign_interrupt(device_t dev, device_t child)
{
ofw_pci_intr_t intr;
int isz;
isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
sizeof(intr));
if (isz != sizeof(intr)) {
/* No property; our best guess is the intpin. */
intr = pci_get_intpin(child);
#ifndef SUN4V
} else if (intr >= 255) {
/*
* A fully specified interrupt (including IGN), as present on
* SPARCengine Ultra AX and E450. Extract the INO and return
* it.
*/
return (INTINO(intr));
#endif
}
/*
* If we got intr from a property, it may or may not be an intpin.
* For on-board devices, it frequently is not, and is completely out
* of the valid intpin range. For PCI slots, it hopefully is,
* otherwise we will have trouble interfacing with non-OFW buses
* such as cardbus.
* Since we cannot tell which it is without violating layering, we
* will always use the route_interrupt method, and treat exceptions
* on the level they become apparent.
*/
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
}
/*
* Tell the hypervisor how to contact us for event channel callbacks.
*/
void
xen_hvm_set_callback(device_t dev)
{
struct xen_hvm_param xhp;
int irq;
if (xen_vector_callback_enabled)
return;
xhp.domid = DOMID_SELF;
xhp.index = HVM_PARAM_CALLBACK_IRQ;
if (xen_feature(XENFEAT_hvm_callback_vector) != 0) {
int error;
error = set_percpu_callback(0);
if (error == 0) {
xen_evtchn_needs_ack = true;
/* Trick toolstack to think we are enlightened */
xhp.value = 1;
} else
xhp.value = HVM_CALLBACK_VECTOR(IDT_EVTCHN);
error = HYPERVISOR_hvm_op(HVMOP_set_param, &xhp);
if (error == 0) {
xen_vector_callback_enabled = 1;
return;
} else if (xen_evtchn_needs_ack)
panic("Unable to setup fake HVM param: %d", error);
printf("Xen HVM callback vector registration failed (%d). "
"Falling back to emulated device interrupt\n", error);
}
xen_vector_callback_enabled = 0;
if (dev == NULL) {
/*
* Called from early boot or resume.
* xenpci will invoke us again later.
*/
return;
}
irq = pci_get_irq(dev);
if (irq < 16) {
xhp.value = HVM_CALLBACK_GSI(irq);
} else {
u_int slot;
u_int pin;
slot = pci_get_slot(dev);
pin = pci_get_intpin(dev) - 1;
xhp.value = HVM_CALLBACK_PCI_INTX(slot, pin);
}
if (HYPERVISOR_hvm_op(HVMOP_set_param, &xhp) != 0)
panic("Can't set evtchn callback");
}
static int
fwohci_pci_init(device_t self)
{
int olatency, latency, ocache_line, cache_line;
uint16_t cmd;
cmd = pci_read_config(self, PCIR_COMMAND, 2);
cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
#if 1 /* for broken hardware */
cmd &= ~PCIM_CMD_MWRICEN;
#endif
pci_write_config(self, PCIR_COMMAND, cmd, 2);
/*
* Some Sun PCIO-2 FireWire controllers have their intpin register
* bogusly set to 0, although it should be 3. Correct that.
*/
if (pci_get_devid(self) == (FW_VENDORID_SUN | FW_DEVICE_PCIO2FW) &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 3);
latency = olatency = pci_read_config(self, PCIR_LATTIMER, 1);
#define DEF_LATENCY 0x20
if (olatency < DEF_LATENCY) {
latency = DEF_LATENCY;
pci_write_config(self, PCIR_LATTIMER, latency, 1);
}
cache_line = ocache_line = pci_read_config(self, PCIR_CACHELNSZ, 1);
#define DEF_CACHE_LINE 8
if (ocache_line < DEF_CACHE_LINE) {
cache_line = DEF_CACHE_LINE;
pci_write_config(self, PCIR_CACHELNSZ, cache_line, 1);
}
if (firewire_debug) {
device_printf(self, "latency timer %d -> %d.\n",
olatency, latency);
device_printf(self, "cache size %d -> %d.\n",
ocache_line, cache_line);
}
return 0;
}
/*
* Tell the hypervisor how to contact us for event channel callbacks.
*/
static void
xenpci_set_callback(device_t dev)
{
int irq;
uint64_t callback;
struct xen_hvm_param xhp;
irq = pci_get_irq(dev);
if (irq < 16) {
callback = irq;
} else {
callback = (pci_get_intpin(dev) - 1) & 3;
callback |= pci_get_slot(dev) << 11;
callback |= 1ull << 56;
}
xhp.domid = DOMID_SELF;
xhp.index = HVM_PARAM_CALLBACK_IRQ;
xhp.value = callback;
if (HYPERVISOR_hvm_op(HVMOP_set_param, &xhp))
panic("Can't set evtchn callback");
}
static int
ofw_pcibus_assign_interrupt(device_t dev, device_t child)
{
ofw_pci_intr_t intr[2];
phandle_t node, iparent;
int isz, icells;
node = ofw_bus_get_node(child);
if (node == -1) {
/* Non-firmware enumerated child, use standard routing */
intr[0] = pci_get_intpin(child);
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
intr[0]));
}
/*
* Try to determine the node's interrupt parent so we know which
* PIC to use.
*/
iparent = -1;
if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) < 0)
iparent = -1;
icells = 1;
if (iparent != -1)
OF_getprop(OF_node_from_xref(iparent), "#interrupt-cells",
&icells, sizeof(icells));
/*
* Any AAPL,interrupts property gets priority and is
* fully specified (i.e. does not need routing)
*/
isz = OF_getprop(node, "AAPL,interrupts", intr, sizeof(intr));
if (isz == sizeof(intr[0])*icells)
return ((iparent == -1) ? intr[0] : ofw_bus_map_intr(dev,
iparent, icells, intr));
isz = OF_getprop(node, "interrupts", intr, sizeof(intr));
if (isz == sizeof(intr[0])*icells) {
if (iparent != -1)
intr[0] = ofw_bus_map_intr(dev, iparent, icells, intr);
} else {
/* No property: our best guess is the intpin. */
intr[0] = pci_get_intpin(child);
}
/*
* If we got intr from a property, it may or may not be an intpin.
* For on-board devices, it frequently is not, and is completely out
* of the valid intpin range. For PCI slots, it hopefully is,
* otherwise we will have trouble interfacing with non-OFW buses
* such as cardbus.
* Since we cannot tell which it is without violating layering, we
* will always use the route_interrupt method, and treat exceptions
* on the level they become apparent.
*/
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr[0]));
}
int
hme_pci_attach(device_t dev)
{
struct hme_pci_softc *hsc;
struct hme_softc *sc;
bus_space_tag_t memt;
bus_space_handle_t memh;
int i, error = 0;
#if !(defined(__powerpc__) || defined(__sparc64__))
device_t *children, ebus_dev;
struct resource *ebus_rres;
int j, slot;
#endif
pci_enable_busmaster(dev);
/*
* Some Sun HMEs do have their intpin register bogusly set to 0,
* although it should be 1. Correct that.
*/
if (pci_get_intpin(dev) == 0)
pci_set_intpin(dev, 1);
hsc = device_get_softc(dev);
sc = &hsc->hsc_hme;
sc->sc_dev = dev;
sc->sc_flags |= HME_PCI;
mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
MTX_DEF);
/*
* Map five register banks:
*
* bank 0: HME SEB registers: +0x0000
* bank 1: HME ETX registers: +0x2000
* bank 2: HME ERX registers: +0x4000
* bank 3: HME MAC registers: +0x6000
* bank 4: HME MIF registers: +0x7000
*
*/
i = PCIR_BAR(0);
hsc->hsc_sres = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (hsc->hsc_sres == NULL) {
device_printf(dev, "could not map device registers\n");
error = ENXIO;
goto fail_mtx;
}
i = 0;
hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&i, RF_SHAREABLE | RF_ACTIVE);
if (hsc->hsc_ires == NULL) {
device_printf(dev, "could not allocate interrupt\n");
error = ENXIO;
goto fail_sres;
}
memt = rman_get_bustag(hsc->hsc_sres);
memh = rman_get_bushandle(hsc->hsc_sres);
sc->sc_sebt = sc->sc_etxt = sc->sc_erxt = sc->sc_mact = sc->sc_mift =
memt;
bus_space_subregion(memt, memh, 0x0000, 0x1000, &sc->sc_sebh);
bus_space_subregion(memt, memh, 0x2000, 0x1000, &sc->sc_etxh);
bus_space_subregion(memt, memh, 0x4000, 0x1000, &sc->sc_erxh);
bus_space_subregion(memt, memh, 0x6000, 0x1000, &sc->sc_mach);
bus_space_subregion(memt, memh, 0x7000, 0x1000, &sc->sc_mifh);
#if defined(__powerpc__) || defined(__sparc64__)
OF_getetheraddr(dev, sc->sc_enaddr);
#else
/*
* Dig out VPD (vital product data) and read NA (network address).
*
* The PCI HME is a PCIO chip, which is composed of two functions:
* function 0: PCI-EBus2 bridge, and
* function 1: HappyMeal Ethernet controller.
*
* The VPD of HME resides in the Boot PROM (PCI FCode) attached
* to the EBus bridge and can't be accessed via the PCI capability
* pointer.
* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
* chapter 2 describes the data structure.
*
* We don't have a MI EBus driver since no EBus device exists
* (besides the FCode PROM) on add-on HME boards. The ``no driver
* attached'' message for function 0 therefore is what is expected.
*/
#define PCI_ROMHDR_SIZE 0x1c
#define PCI_ROMHDR_SIG 0x00
#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
#define PCI_ROMHDR_PTR_DATA 0x18
#define PCI_ROM_SIZE 0x18
#define PCI_ROM_SIG 0x00
#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
/* reversed */
#define PCI_ROM_VENDOR 0x04
#define PCI_ROM_DEVICE 0x06
#define PCI_ROM_PTR_VPD 0x08
#define PCI_VPDRES_BYTE0 0x00
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
#define PCI_VPDRES_LARGE_LEN_LSB 0x01
#define PCI_VPDRES_LARGE_LEN_MSB 0x02
#define PCI_VPDRES_LARGE_DATA 0x03
#define PCI_VPD_SIZE 0x03
#define PCI_VPD_KEY0 0x00
#define PCI_VPD_KEY1 0x01
#define PCI_VPD_LEN 0x02
#define PCI_VPD_DATA 0x03
#define HME_ROM_READ_N(n, offs) bus_space_read_ ## n (memt, memh, (offs))
#define HME_ROM_READ_1(offs) HME_ROM_READ_N(1, (offs))
#define HME_ROM_READ_2(offs) HME_ROM_READ_N(2, (offs))
#define HME_ROM_READ_4(offs) HME_ROM_READ_N(4, (offs))
/* Search accompanying EBus bridge. */
slot = pci_get_slot(dev);
if (device_get_children(device_get_parent(dev), &children, &i) != 0) {
device_printf(dev, "could not get children\n");
error = ENXIO;
goto fail_sres;
}
ebus_dev = NULL;
for (j = 0; j < i; j++) {
if (pci_get_class(children[j]) == PCIC_BRIDGE &&
pci_get_vendor(children[j]) == PCI_VENDOR_SUN &&
pci_get_device(children[j]) == PCI_PRODUCT_SUN_EBUS &&
pci_get_slot(children[j]) == slot) {
ebus_dev = children[j];
break;
}
}
if (ebus_dev == NULL) {
device_printf(dev, "could not find EBus bridge\n");
error = ENXIO;
goto fail_children;
}
/* Map EBus bridge PROM registers. */
i = PCIR_BAR(0);
if ((ebus_rres = bus_alloc_resource_any(ebus_dev, SYS_RES_MEMORY,
&i, RF_ACTIVE)) == NULL) {
device_printf(dev, "could not map PROM registers\n");
error = ENXIO;
goto fail_children;
}
memt = rman_get_bustag(ebus_rres);
memh = rman_get_bushandle(ebus_rres);
/* Read PCI Expansion ROM header. */
if (HME_ROM_READ_2(PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
(i = HME_ROM_READ_2(PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM header\n");
error = ENXIO;
goto fail_rres;
}
/* Read PCI Expansion ROM data. */
if (HME_ROM_READ_4(i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
HME_ROM_READ_2(i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
HME_ROM_READ_2(i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
(j = HME_ROM_READ_2(i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM data\n");
error = ENXIO;
goto fail_rres;
}
/*
* Read PCI VPD.
* SUNW,hme cards have a single large resource VPD-R tag
* containing one NA. SUNW,qfe cards have four large resource
* VPD-R tags containing one NA each (all four HME chips share
* the same PROM).
* The VPD used on both cards is not in PCI 2.2 standard format
* however. The length in the resource header is in big endian
* and the end tag is non-standard (0x79) and followed by an
* all-zero "checksum" byte. Sun calls this a "Fresh Choice
* Ethernet" VPD...
*/
/* Look at the end tag to determine whether this is a VPD with 4 NAs. */
if (HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN) != 0x79 &&
HME_ROM_READ_1(j + 4 * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN)) == 0x79)
/* Use the Nth NA for the Nth HME on this SUNW,qfe. */
j += slot * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
ETHER_ADDR_LEN);
if (PCI_VPDRES_ISLARGE(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) == 0 ||
PCI_VPDRES_LARGE_NAME(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) !=
PCI_VPDRES_TYPE_VPD ||
(HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_LSB) << 8 |
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_MSB)) !=
PCI_VPD_SIZE + ETHER_ADDR_LEN ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY0) !=
0x4e /* N */ ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY1) !=
0x41 /* A */ ||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_LEN) !=
ETHER_ADDR_LEN) {
device_printf(dev, "unexpected PCI VPD\n");
error = ENXIO;
goto fail_rres;
}
bus_space_read_region_1(memt, memh, j + PCI_VPDRES_LARGE_DATA +
PCI_VPD_DATA, sc->sc_enaddr, ETHER_ADDR_LEN);
fail_rres:
bus_release_resource(ebus_dev, SYS_RES_MEMORY,
rman_get_rid(ebus_rres), ebus_rres);
fail_children:
free(children, M_TEMP);
if (error != 0)
goto fail_sres;
#endif
sc->sc_burst = 64; /* XXX */
/*
* call the main configure
*/
if ((error = hme_config(sc)) != 0) {
device_printf(dev, "could not be configured\n");
goto fail_ires;
}
if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET |
INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) {
device_printf(dev, "couldn't establish interrupt\n");
hme_detach(sc);
goto fail_ires;
}
return (0);
fail_ires:
bus_release_resource(dev, SYS_RES_IRQ,
rman_get_rid(hsc->hsc_ires), hsc->hsc_ires);
fail_sres:
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(hsc->hsc_sres), hsc->hsc_sres);
fail_mtx:
mtx_destroy(&sc->sc_lock);
return (error);
}
static int
ohci_pci_attach(device_t self)
{
ohci_softc_t *sc = device_get_softc(self);
int err;
int rid;
/* XXX where does it say so in the spec? */
sc->sc_bus.usbrev = USBREV_1_0;
pci_enable_busmaster(self);
/*
* Some Sun PCIO-2 USB controllers have their intpin register
* bogusly set to 0, although it should be 4. Correct that.
*/
if (pci_get_devid(self) == PCI_OHCI_DEVICEID_PCIO2USB &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 4);
rid = PCI_CBMEM;
sc->io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->io_res) {
device_printf(self, "Could not map memory\n");
return ENXIO;
}
sc->iot = rman_get_bustag(sc->io_res);
sc->ioh = rman_get_bushandle(sc->io_res);
rid = 0;
sc->irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
ohci_pci_detach(self);
return ENXIO;
}
sc->sc_bus.bdev = device_add_child(self, "usb", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
ohci_pci_detach(self);
return ENOMEM;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/* ohci_pci_match will never return NULL if ohci_pci_probe succeeded */
device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_OHCI_VENDORID_ACERLABS:
ksprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_OHCI_VENDORID_AMD:
ksprintf(sc->sc_vendor, "AMD");
break;
case PCI_OHCI_VENDORID_APPLE:
ksprintf(sc->sc_vendor, "Apple");
break;
case PCI_OHCI_VENDORID_ATI:
ksprintf(sc->sc_vendor, "ATI");
break;
case PCI_OHCI_VENDORID_CMDTECH:
ksprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_OHCI_VENDORID_NEC:
ksprintf(sc->sc_vendor, "NEC");
break;
case PCI_OHCI_VENDORID_NVIDIA:
case PCI_OHCI_VENDORID_NVIDIA2:
ksprintf(sc->sc_vendor, "nVidia");
break;
case PCI_OHCI_VENDORID_OPTI:
ksprintf(sc->sc_vendor, "OPTi");
break;
case PCI_OHCI_VENDORID_SIS:
ksprintf(sc->sc_vendor, "SiS");
break;
default:
if (bootverbose)
device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
ksprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
err = bus_setup_intr(self, sc->irq_res, 0,
(driver_intr_t *) ohci_intr, sc, &sc->ih, NULL);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->ih = NULL;
ohci_pci_detach(self);
return ENXIO;
}
/*
* OHCI interrupts which occur early will leave them disabled,
* so run the interrupt manually once we're done with the init.
*/
err = ohci_init(sc);
if (err == 0)
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(self, "USB init failed\n");
ohci_pci_detach(self);
return EIO;
}
return 0;
}
static int
ohci_pci_attach(device_t self)
{
ohci_softc_t *sc = device_get_softc(self);
int err;
int rid;
/* XXX where does it say so in the spec? */
sc->sc_bus.usbrev = USBREV_1_0;
pci_enable_busmaster(self);
/*
* Some Sun PCIO-2 USB controllers have their intpin register
* bogusly set to 0, although it should be 4. Correct that.
*/
if (pci_get_devid(self) == PCI_OHCI_DEVICEID_PCIO2USB &&
pci_get_intpin(self) == 0)
pci_set_intpin(self, 4);
rid = PCI_CBMEM;
sc->io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->io_res) {
device_printf(self, "Could not map memory\n");
return ENXIO;
}
sc->iot = rman_get_bustag(sc->io_res);
sc->ioh = rman_get_bushandle(sc->io_res);
rid = 0;
sc->irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
ohci_pci_detach(self);
return ENXIO;
}
sc->sc_bus.bdev = device_add_child(self, "usb", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
ohci_pci_detach(self);
return ENOMEM;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/* ohci_pci_match will never return NULL if ohci_pci_probe succeeded */
device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_OHCI_VENDORID_ACERLABS:
sprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_OHCI_VENDORID_AMD:
sprintf(sc->sc_vendor, "AMD");
break;
case PCI_OHCI_VENDORID_APPLE:
sprintf(sc->sc_vendor, "Apple");
break;
case PCI_OHCI_VENDORID_ATI:
sprintf(sc->sc_vendor, "ATI");
break;
case PCI_OHCI_VENDORID_CMDTECH:
sprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_OHCI_VENDORID_NEC:
sprintf(sc->sc_vendor, "NEC");
break;
case PCI_OHCI_VENDORID_NVIDIA:
case PCI_OHCI_VENDORID_NVIDIA2:
sprintf(sc->sc_vendor, "nVidia");
break;
case PCI_OHCI_VENDORID_OPTI:
sprintf(sc->sc_vendor, "OPTi");
break;
case PCI_OHCI_VENDORID_SIS:
sprintf(sc->sc_vendor, "SiS");
break;
default:
if (bootverbose)
device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
sprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
err = bus_setup_intr(self, sc->irq_res, INTR_TYPE_BIO, NULL, ohci_intr,
sc, &sc->ih);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->ih = NULL;
ohci_pci_detach(self);
return ENXIO;
}
/* Allocate a parent dma tag for DMA maps */
err = bus_dma_tag_create(bus_get_dma_tag(self), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, USB_DMA_NSEG, BUS_SPACE_MAXSIZE_32BIT, 0,
NULL, NULL, &sc->sc_bus.parent_dmatag);
if (err) {
device_printf(self, "Could not allocate parent DMA tag (%d)\n",
err);
ohci_pci_detach(self);
return ENXIO;
}
/* Allocate a dma tag for transfer buffers */
err = bus_dma_tag_create(sc->sc_bus.parent_dmatag, 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXSIZE_32BIT, USB_DMA_NSEG, BUS_SPACE_MAXSIZE_32BIT, 0,
busdma_lock_mutex, &Giant, &sc->sc_bus.buffer_dmatag);
if (err) {
device_printf(self, "Could not allocate transfer tag (%d)\n",
err);
ohci_pci_detach(self);
return ENXIO;
}
err = ohci_init(sc);
if (!err) {
sc->sc_flags |= OHCI_SCFLG_DONEINIT;
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed\n");
ohci_pci_detach(self);
return EIO;
}
return 0;
}
static int
gem_pci_attach(device_t dev)
{
struct gem_softc *sc;
int i;
#if defined(__powerpc__) || defined(__sparc64__)
char buf[sizeof(GEM_SHARED_PINS)];
#else
int j;
#endif
sc = device_get_softc(dev);
sc->sc_variant = GEM_UNKNOWN;
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
sc->sc_variant = gem_pci_devlist[i].gpd_variant;
break;
}
}
if (sc->sc_variant == GEM_UNKNOWN) {
device_printf(dev, "unknown adaptor\n");
return (ENXIO);
}
pci_enable_busmaster(dev);
/*
* Some Sun GEMs/ERIs do have their intpin register bogusly set to 0,
* although it should be 1. Correct that.
*/
if (pci_get_intpin(dev) == 0)
pci_set_intpin(dev, 1);
/* Set the PCI latency timer for Sun ERIs. */
if (sc->sc_variant == GEM_SUN_ERI)
pci_write_config(dev, PCIR_LATTIMER, GEM_ERI_LATENCY_TIMER, 1);
sc->sc_dev = dev;
sc->sc_flags |= GEM_PCI;
if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
device_printf(dev, "failed to allocate resources\n");
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
return (ENXIO);
}
GEM_LOCK_INIT(sc, device_get_nameunit(dev));
/*
* Derive GEM_RES_BANK2 from GEM_RES_BANK1. This seemed cleaner
* with the old way of using copies of the bus tag and handle in
* the softc along with bus_space_*()...
*/
sc->sc_res[GEM_RES_BANK2] = malloc(sizeof(*sc->sc_res[GEM_RES_BANK2]),
M_DEVBUF, M_NOWAIT | M_ZERO);
if (sc->sc_res[GEM_RES_BANK2] == NULL) {
device_printf(dev, "failed to allocate bank2 resource\n");
goto fail;
}
rman_set_bustag(sc->sc_res[GEM_RES_BANK2],
rman_get_bustag(sc->sc_res[GEM_RES_BANK1]));
bus_space_subregion(rman_get_bustag(sc->sc_res[GEM_RES_BANK1]),
rman_get_bushandle(sc->sc_res[GEM_RES_BANK1]),
GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE,
&sc->sc_res[GEM_RES_BANK2]->r_bushandle);
/* Determine whether we're running at 66MHz. */
if ((GEM_BANK2_READ_4(sc, GEM_PCI_BIF_CONFIG) &
GEM_PCI_BIF_CNF_M66EN) != 0)
sc->sc_flags |= GEM_PCI66;
#if defined(__powerpc__) || defined(__sparc64__)
OF_getetheraddr(dev, sc->sc_enaddr);
if (OF_getprop(ofw_bus_get_node(dev), GEM_SHARED_PINS, buf,
sizeof(buf)) > 0) {
buf[sizeof(buf) - 1] = '\0';
if (strcmp(buf, GEM_SHARED_PINS_SERDES) == 0)
sc->sc_flags |= GEM_SERDES;
}
#else
/*
* Dig out VPD (vital product data) and read NA (network address).
* The VPD resides in the PCI Expansion ROM (PCI FCode) and can't
* be accessed via the PCI capability pointer.
* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
* chapter 2 describes the data structure.
*/
#define PCI_ROMHDR_SIZE 0x1c
#define PCI_ROMHDR_SIG 0x00
#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
#define PCI_ROMHDR_PTR_DATA 0x18
#define PCI_ROM_SIZE 0x18
#define PCI_ROM_SIG 0x00
#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
/* reversed */
#define PCI_ROM_VENDOR 0x04
#define PCI_ROM_DEVICE 0x06
#define PCI_ROM_PTR_VPD 0x08
#define PCI_VPDRES_BYTE0 0x00
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
#define PCI_VPDRES_LARGE_LEN_LSB 0x01
#define PCI_VPDRES_LARGE_LEN_MSB 0x02
#define PCI_VPDRES_LARGE_SIZE 0x03
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
#define PCI_VPD_KEY0 0x00
#define PCI_VPD_KEY1 0x01
#define PCI_VPD_LEN 0x02
#define PCI_VPD_SIZE 0x03
#define GEM_ROM_READ_1(sc, offs) \
GEM_BANK1_READ_1((sc), GEM_PCI_ROM_OFFSET + (offs))
#define GEM_ROM_READ_2(sc, offs) \
GEM_BANK1_READ_2((sc), GEM_PCI_ROM_OFFSET + (offs))
#define GEM_ROM_READ_4(sc, offs) \
GEM_BANK1_READ_4((sc), GEM_PCI_ROM_OFFSET + (offs))
/* Read PCI Expansion ROM header. */
if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
(i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
PCI_ROMHDR_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM header\n");
goto fail;
}
/* Read PCI Expansion ROM data. */
if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
(j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
i + PCI_ROM_SIZE) {
device_printf(dev, "unexpected PCI Expansion ROM data\n");
goto fail;
}
/*
* Read PCI VPD.
* SUNW,pci-gem cards have a single large resource VPD-R tag
* containing one NA. The VPD used is not in PCI 2.2 standard
* format however. The length in the resource header is in big
* endian and the end tag is non-standard (0x79) and followed
* by an all-zero "checksum" byte. Sun calls this a "Fresh
* Choice Ethernet" VPD...
*/
if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
j + PCI_VPDRES_BYTE0)) == 0 ||
PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD ||
((GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8) |
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
PCI_VPD_SIZE + ETHER_ADDR_LEN ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY0) !=
0x4e /* N */ ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_KEY1) !=
0x41 /* A */ ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_LEN) !=
ETHER_ADDR_LEN ||
GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE +
ETHER_ADDR_LEN) != 0x79) {
device_printf(dev, "unexpected PCI VPD\n");
goto fail;
}
bus_read_region_1(sc->sc_res[GEM_RES_BANK1],
GEM_PCI_ROM_OFFSET + j + PCI_VPDRES_LARGE_SIZE + PCI_VPD_SIZE,
sc->sc_enaddr, ETHER_ADDR_LEN);
#endif
/*
* The Xserve G5 has a fake GMAC with an all-zero MAC address.
* Check for this, and don't attach in this case.
*/
for (i = 0; i < ETHER_ADDR_LEN && sc->sc_enaddr[i] == 0; i++) {}
if (i == ETHER_ADDR_LEN) {
device_printf(dev, "invalid MAC address\n");
goto fail;
}
if (gem_attach(sc) != 0) {
device_printf(dev, "could not be attached\n");
goto fail;
}
if (bus_setup_intr(dev, sc->sc_res[GEM_RES_INTR], INTR_TYPE_NET |
INTR_MPSAFE, NULL, gem_intr, sc, &sc->sc_ih) != 0) {
device_printf(dev, "failed to set up interrupt\n");
gem_detach(sc);
goto fail;
}
return (0);
fail:
if (sc->sc_res[GEM_RES_BANK2] != NULL)
free(sc->sc_res[GEM_RES_BANK2], M_DEVBUF);
GEM_LOCK_DESTROY(sc);
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
return (ENXIO);
}
static int
ohci_pci_attach(device_t self)
{
ohci_softc_t *sc = device_get_softc(self);
int rid;
int err;
/* initialise some bus fields */
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = OHCI_MAX_DEVICES;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self),
&ohci_iterate_hw_softc)) {
return (ENOMEM);
}
sc->sc_dev = self;
pci_enable_busmaster(self);
/*
* Some Sun PCIO-2 USB controllers have their intpin register
* bogusly set to 0, although it should be 4. Correct that.
*/
if (pci_get_devid(self) == 0x1103108e && pci_get_intpin(self) == 0)
pci_set_intpin(self, 4);
rid = PCI_CBMEM;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = rman_get_size(sc->sc_io_res);
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
/*
* ohci_pci_match will never return NULL if ohci_pci_probe
* succeeded
*/
device_set_desc(sc->sc_bus.bdev, ohci_pci_match(self));
switch (pci_get_vendor(self)) {
case PCI_OHCI_VENDORID_ACERLABS:
sprintf(sc->sc_vendor, "AcerLabs");
break;
case PCI_OHCI_VENDORID_AMD:
sprintf(sc->sc_vendor, "AMD");
break;
case PCI_OHCI_VENDORID_APPLE:
sprintf(sc->sc_vendor, "Apple");
break;
case PCI_OHCI_VENDORID_ATI:
sprintf(sc->sc_vendor, "ATI");
break;
case PCI_OHCI_VENDORID_CMDTECH:
sprintf(sc->sc_vendor, "CMDTECH");
break;
case PCI_OHCI_VENDORID_NEC:
sprintf(sc->sc_vendor, "NEC");
break;
case PCI_OHCI_VENDORID_NVIDIA:
case PCI_OHCI_VENDORID_NVIDIA2:
sprintf(sc->sc_vendor, "nVidia");
break;
case PCI_OHCI_VENDORID_OPTI:
sprintf(sc->sc_vendor, "OPTi");
break;
case PCI_OHCI_VENDORID_SIS:
sprintf(sc->sc_vendor, "SiS");
break;
case PCI_OHCI_VENDORID_SUN:
sprintf(sc->sc_vendor, "SUN");
break;
default:
if (bootverbose) {
device_printf(self, "(New OHCI DeviceId=0x%08x)\n",
pci_get_devid(self));
}
sprintf(sc->sc_vendor, "(0x%04x)", pci_get_vendor(self));
}
/* sc->sc_bus.usbrev; set by ohci_init() */
#if (__FreeBSD_version >= 700031)
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)ohci_interrupt, sc, &sc->sc_intr_hdl);
#else
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
(driver_intr_t *)ohci_interrupt, sc, &sc->sc_intr_hdl);
#endif
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
err = ohci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed\n");
goto error;
}
return (0);
error:
ohci_pci_detach(self);
return (ENXIO);
}
