static int set_int_cnt(int chan) {
/* Write interrupt count for specified channel.
After <DspFragmentSize> bytes, an interrupt will be generated */
int sample_count;
u16_t int_cnt_reg;
if (aud_conf[chan].fragment_size >
(sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments)
|| aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) {
return EINVAL;
}
switch(chan) {
case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break;
case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break;
case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break;
default: return EINVAL;
}
sample_count = aud_conf[chan].fragment_size;
/* adjust sample count according to sample format */
if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1;
switch(aud_conf[chan].nr_of_bits) {
case 16: sample_count >>= 1;break;
case 8: break;
default: return EINVAL;
}
/* set the sample count - 1 for the specified channel. */
pci_outw(reg(int_cnt_reg), sample_count - 1);
return OK;
}
PUBLIC int drv_init_hw (void) {
u16_t i, j;
u16_t chip_sel_ctrl_reg;
/* First, detect the hardware */
if (detect_hw() != OK) {
return EIO;
}
/* PCI command register
* enable the SERR# driver, PCI bus mastering and I/O access
*/
pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS);
/* turn everything off */
pci_outl(reg(CHIP_SEL_CTRL), 0x0UL);
/* turn off legacy (legacy control is undocumented) */
pci_outl(reg(LEGACY), 0x0UL);
pci_outl(reg(LEGACY+4), 0x0UL);
/* turn off serial interface */
pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL);
/*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/
/* enable the codec */
chip_sel_ctrl_reg = pci_inw(reg(CHIP_SEL_CTRL));
chip_sel_ctrl_reg |= XCTL0 | CDC_EN;
pci_outw(reg(CHIP_SEL_CTRL), chip_sel_ctrl_reg);
/* initialize the codec */
if (ak4531_init(reg(CODEC_WRITE_ADDRESS),
reg(INTERRUPT_STATUS), CWRIP, reg(0)) < 0) {
return EINVAL;
}
/* clear all the memory */
for (i = 0; i < 0x10; ++i) {
pci_outb(reg(MEM_PAGE), i);
for (j = 0; j < 0x10; j += 4) {
pci_outl (reg(MEMORY) + j, 0x0UL);
}
}
/* initialize variables for each sub_device */
for (i = 0; i < drv.NrOfSubDevices; i++) {
if(i != MIXER) {
aud_conf[i].busy = 0;
aud_conf[i].stereo = DEFAULT_STEREO;
aud_conf[i].sample_rate = DEFAULT_RATE;
aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS;
aud_conf[i].sign = DEFAULT_SIGNED;
aud_conf[i].fragment_size =
sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments;
}
}
return OK;
}
int drv_reenable_int(int chan) {
u16_t ser_interface, int_en_bit;
switch(chan) {
case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;
default: return EINVAL;
}
/* clear and reenable an interrupt */
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit);
return OK;
}
DMPAPI(void) pci_Out16(void* handle, unsigned char offset, unsigned short val) {
PCI_BASE_t* base = (PCI_BASE_t*)handle;
io_DisableINT();
//pci_outw(base->addr + (unsigned long)(offset & 0xfe), val);
pci_outw(base->addr + (unsigned long)offset, val); // assume offset % 4 < 3
io_RestoreINT();
}
PRIVATE int ak4531_write (u8_t address, u8_t data) {
u16_t to_be_written;
if (address < MASTER_VOLUME_LCH || address > MIC_AMP_GAIN) return -1;
to_be_written = (u16_t)((address << 8) | data);
if (!ak4531_finished()) return -1;
pci_outw(base_address, to_be_written);
return 0;
}
int drv_stop(int sub_dev)
{
u32_t enable_bit;
switch(sub_dev) {
case ADC1_CHAN: enable_bit = ADC1_EN;break;
case DAC1_CHAN: enable_bit = DAC1_EN;break;
case DAC2_CHAN: enable_bit = DAC2_EN;break;
default: return EINVAL;
}
/* stop the specified channel */
pci_outw(reg(CHIP_SEL_CTRL),
pci_inw(reg(CHIP_SEL_CTRL)) & ~enable_bit);
aud_conf[sub_dev].busy = 0;
disable_int(sub_dev);
return OK;
}
static int set_stereo(u32_t stereo, int sub_dev) {
/* set format bits for specified channel. */
u16_t stereo_bit, ser_interface;
switch(sub_dev) {
case ADC1_CHAN: stereo_bit = R1_S_MB; break;
case DAC1_CHAN: stereo_bit = P1_S_MB; break;
case DAC2_CHAN: stereo_bit = P2_S_MB; break;
default: return EINVAL;
}
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
ser_interface &= ~stereo_bit;
if (stereo) {
ser_interface |= stereo_bit;
}
pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
aud_conf[sub_dev].stereo = stereo;
return OK;
}
static int set_bits(u32_t nr_of_bits, int sub_dev) {
/* set format bits for specified channel. */
u16_t size_16_bit, ser_interface;
switch(sub_dev) {
case ADC1_CHAN: size_16_bit = R1_S_EB; break;
case DAC1_CHAN: size_16_bit = P1_S_EB; break;
case DAC2_CHAN: size_16_bit = P2_S_EB; break;
default: return EINVAL;
}
ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
ser_interface &= ~size_16_bit;
switch(nr_of_bits) {
case 16: ser_interface |= size_16_bit;break;
case 8: break;
default: return EINVAL;
}
pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
aud_conf[sub_dev].nr_of_bits = nr_of_bits;
return OK;
}
int drv_start(int sub_dev, int UNUSED(DmaMode)) {
u32_t enable_bit, result = 0;
/* Write default values to device in case user failed to configure.
If user did configure properly, everything is written twice.
please raise your hand if you object against to this strategy...*/
result |= set_sample_rate(aud_conf[sub_dev].sample_rate, sub_dev);
result |= set_stereo(aud_conf[sub_dev].stereo, sub_dev);
result |= set_bits(aud_conf[sub_dev].nr_of_bits, sub_dev);
result |= set_sign(aud_conf[sub_dev].sign, sub_dev);
/* set the interrupt count */
result |= set_int_cnt(sub_dev);
if (result) {
return EIO;
}
/* if device currently paused, resume */
drv_resume(sub_dev);
switch(sub_dev) {
case ADC1_CHAN: enable_bit = ADC1_EN;break;
case DAC1_CHAN: enable_bit = DAC1_EN;break;
case DAC2_CHAN: enable_bit = DAC2_EN;break;
default: return EINVAL;
}
/* enable interrupts from 'sub device' */
drv_reenable_int(sub_dev);
/* this means play!!! */
pci_outw(reg(CHIP_SEL_CTRL), pci_inw(reg(CHIP_SEL_CTRL)) | enable_bit);
aud_conf[sub_dev].busy = 1;
return OK;
}
void ahi_pci_outw(UWORD value, ULONG addr, APTR dev)
{
pci_outw(SWAPWORD(value), addr);
}