/* * Compare PCI device parameters (vendor id, device id, subsystem id, etc) * with those specified in the struct pci_dev_t. vid and did of the struct * must be defined. * * Return TRUE on match, FALSE if else. */ int pci_device_match(struct pci_entry_t *e, struct pci_dev_t *c) { u_int32_t data; /* These must be defined */ data = pci_read_reg(e, PCI_ID_REG); #ifdef DEBUG if (data != 0xFFFFFFFF) { printf("bus %u, dev %u, fun %u:", e->bus, e->dev, e->fun); printf("\tvendor id 0x%x, product id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data)); } #endif /* DEBUG */ if (PCI_PRODUCT(data) != c->did) return 0; if (PCI_VENDOR(data) != c->vid) return 0; #ifdef DEBUG printf("bus %u, dev %u, fun %u:", e->bus, e->dev, e->fun); printf("\tvendor id 0x%x, product id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data)); data = pci_read_reg(e, PCI_CLASS_REG); printf("\tclass multimedia, subclass 0x%x, revision 0x%x\n", PCI_SUBCLASS(data), PCI_REVISION(data)); data = pci_read_reg(e, PCI_SUBSYSVEND_REG); printf("\tsubsystem vendor id 0x%x, subsystem id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data)); #endif /* DEBUG */ data = pci_read_reg(e, PCI_CLASS_REG); if (PCI_CLASS(data) != PCI_CLASS_MULTIMEDIA) return 0; if (c->subclass != PCI_SUBCLASS_ANY) if (c->subclass != PCI_SUBCLASS(data)) return 0; if (c->rev != PCI_REVISION_ANY) if (c->rev != PCI_REVISION(data)) return 0; data = pci_read_reg(e, PCI_SUBSYSVEND_REG); if (c->subvid != PCI_SUBSYS_ID_ANY) if (c->subvid != PCI_VENDOR(data)) return 0; if (c->subdid != PCI_SUBSYS_ID_ANY) if (c->subdid != PCI_PRODUCT(data)) return 0; return 1; }
static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) { int shift = 8 * (where & 3); u32 val = pci_read_reg(pcie, where & ~3); return val >> shift; }
static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) { int shift = 8 * (where & 3); u32 val = pci_read_reg(pcie, where & ~3); val &= ~(mask << shift); val |= data << shift; pci_write_reg(pcie, val, where & ~3); }
/* * Initialization. Try all known PCI access methods. Note that we support * using both PCI BIOS and direct access: in such cases, we use I/O ports * to access config space. * * Note that the platform specific initialization (BSC registers, and memory * space mapping) will be called via the platform defined function * pcibios_init_platform(). */ static int __init sh7780_pci_init(void) { unsigned int id; int ret, match = 0; pr_debug("PCI: Starting intialization.\n"); ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ /* check for SH7780/SH7780R hardware */ id = pci_read_reg(SH7780_PCIVID); if ((id & 0xffff) == SH7780_VENDOR_ID) { switch ((id >> 16) & 0xffff) { case SH7763_DEVICE_ID: case SH7780_DEVICE_ID: case SH7781_DEVICE_ID: case SH7785_DEVICE_ID: match = 1; break; } } if (unlikely(!match)) { printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); return -ENODEV; } /* Setup the INTC */ if (mach_is_7780se()) { /* ICR0: IRL=use separately */ ctrl_outl(0x00C00020, INTC_ICR0); /* ICR1: detect low level(for 2ndcut) */ ctrl_outl(0xAAAA0000, INTC_ICR1); /* INTPRI: priority=3(all) */ ctrl_outl(0x33333333, INTC_INTPRI); } if ((ret = sh4_pci_check_direct()) != 0) return ret; return pcibios_init_platform(); }
/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ static int rcar_pcie_config_access(struct rcar_pcie *pcie, unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { int dev, func, reg, index; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); reg = where & ~3; index = reg / 4; /* * While each channel has its own memory-mapped extended config * space, it's generally only accessible when in endpoint mode. * When in root complex mode, the controller is unable to target * itself with either type 0 or type 1 accesses, and indeed, any * controller initiated target transfer to its own config space * result in a completer abort. * * Each channel effectively only supports a single device, but as * the same channel <-> device access works for any PCI_SLOT() * value, we cheat a bit here and bind the controller's config * space to devfn 0 in order to enable self-enumeration. In this * case the regular ECAR/ECDR path is sidelined and the mangled * config access itself is initiated as an internal bus transaction. */ if (pci_is_root_bus(bus)) { if (dev != 0) return PCIBIOS_DEVICE_NOT_FOUND; if (access_type == PCI_ACCESS_READ) { *data = pci_read_reg(pcie, PCICONF(index)); } else { /* Keep an eye out for changes to the root bus number */ if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) pcie->root_bus_nr = *data & 0xff; pci_write_reg(pcie, *data, PCICONF(index)); } return PCIBIOS_SUCCESSFUL; } if (pcie->root_bus_nr < 0) return PCIBIOS_DEVICE_NOT_FOUND; /* Clear errors */ pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); /* Set the PIO address */ pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); /* Enable the configuration access */ if (bus->parent->number == pcie->root_bus_nr) pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR); else pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR); /* Check for errors */ if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) return PCIBIOS_DEVICE_NOT_FOUND; /* Check for master and target aborts */ if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) return PCIBIOS_DEVICE_NOT_FOUND; if (access_type == PCI_ACCESS_READ) *data = pci_read_reg(pcie, PCIECDR); else pci_write_reg(pcie, *data, PCIECDR); /* Disable the configuration access */ pci_write_reg(pcie, 0, PCIECCTLR); return PCIBIOS_SUCCESSFUL; }
static int sh7786_pcie_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { struct pci_channel *chan = bus->sysdata; int dev, func, type, reg; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); type = !!bus->parent; reg = where & ~3; if (bus->number > 255 || dev > 31 || func > 7) return PCIBIOS_FUNC_NOT_SUPPORTED; /* * While each channel has its own memory-mapped extended config * space, it's generally only accessible when in endpoint mode. * When in root complex mode, the controller is unable to target * itself with either type 0 or type 1 accesses, and indeed, any * controller initiated target transfer to its own config space * result in a completer abort. * * Each channel effectively only supports a single device, but as * the same channel <-> device access works for any PCI_SLOT() * value, we cheat a bit here and bind the controller's config * space to devfn 0 in order to enable self-enumeration. In this * case the regular PAR/PDR path is sidelined and the mangled * config access itself is initiated as a SuperHyway transaction. */ if (pci_is_root_bus(bus)) { if (dev == 0) { if (access_type == PCI_ACCESS_READ) *data = pci_read_reg(chan, PCI_REG(reg)); else pci_write_reg(chan, *data, PCI_REG(reg)); return PCIBIOS_SUCCESSFUL; } else if (dev > 1) return PCIBIOS_DEVICE_NOT_FOUND; } /* Clear errors */ pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR); /* Set the PIO address */ pci_write_reg(chan, (bus->number << 24) | (dev << 19) | (func << 16) | reg, SH4A_PCIEPAR); /* Enable the configuration access */ pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR); /* Check for errors */ if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; /* Check for master and target aborts */ if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) return PCIBIOS_DEVICE_NOT_FOUND; if (access_type == PCI_ACCESS_READ) *data = pci_read_reg(chan, SH4A_PCIEPDR); else pci_write_reg(chan, *data, SH4A_PCIEPDR); /* Disable the configuration access */ pci_write_reg(chan, 0, SH4A_PCIEPCTLR); return PCIBIOS_SUCCESSFUL; }
/* * Return base address of a PCI device specified in the struct pci_entry_t */ u_int16_t pci_base_addr(struct pci_entry_t *c) { return pci_read_reg(c, PCI_BASEADDR_0); }