void __init
pplus_setup_hose(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = PREP_ISA_MEM_BASE;
hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
pplus_init_resource(&hose->io_resource, 0x00000000, 0x0fffffff,
IORESOURCE_IO);
pplus_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfdffffff,
IORESOURCE_MEM);
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0fffffff;
hose->mem_space.start = 0x00000000;
hose->mem_space.end = 0x3cfbffff; /* MPIC at 0x3cfc0000-0x3dffffff */
setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
pplus_set_VIA_IDE_legacy();
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = pplus_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
pplus_set_board_type();
}
static void __init
yosemite_setup_hose(void)
{
unsigned int bar_response, bar;
struct pci_controller *hose;
yosemite_setup_pci();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = YOSEMITE_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
YOSEMITE_PCI_LOWER_IO,
YOSEMITE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
YOSEMITE_PCI_LOWER_MEM,
YOSEMITE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
ppc_md.pci_exclude_device = yosemite_exclude_device;
hose->io_space.start = YOSEMITE_PCI_LOWER_IO;
hose->io_space.end = YOSEMITE_PCI_UPPER_IO;
hose->mem_space.start = YOSEMITE_PCI_LOWER_MEM;
hose->mem_space.end = YOSEMITE_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(YOSEMITE_PCI_IO_BASE, YOSEMITE_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
YOSEMITE_PCI_CFGA_PLB32,
YOSEMITE_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
/* Zero config bars */
for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
early_write_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
0x00000000);
early_read_config_dword(hose, hose->first_busno,
PCI_FUNC(hose->first_busno), bar,
&bar_response);
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yosemite_map_irq;
}
static void __init
sandpoint_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
if (mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B, MPC10X_MAPB_EUMB_BASE) == 0) {
/* Do early winbond init, then scan PCI bus */
sandpoint_setup_winbond_83553(hose);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = sandpoint_map_irq;
} else {
if (ppc_md.progress)
ppc_md.progress("Bridge init failed", 0x100);
printk("Host bridge init failed\n");
}
return;
}
static int __init storcenter_add_bridge(struct device_node *dev)
{
#ifdef CONFIG_PCI
int len;
struct pci_controller *hose;
const int *bus_range;
printk("Adding PCI host bridge %s\n", dev->full_name);
hose = pcibios_alloc_controller(dev);
if (hose == NULL)
return -ENOMEM;
bus_range = of_get_property(dev, "bus-range", &len);
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, 1);
#endif
return 0;
}
void __init efika_pcisetup(void)
{
const int *bus_range;
int len;
struct pci_controller *hose;
struct device_node *root;
struct device_node *pcictrl;
root = of_find_node_by_path("/");
if (root == NULL) {
printk(KERN_WARNING EFIKA_PLATFORM_NAME
": Unable to find the root node\n");
return;
}
for (pcictrl = NULL;;) {
pcictrl = of_get_next_child(root, pcictrl);
if ((pcictrl == NULL) || (strcmp(pcictrl->name, "pci") == 0))
break;
}
of_node_put(root);
if (pcictrl == NULL) {
printk(KERN_WARNING EFIKA_PLATFORM_NAME
": Unable to find the PCI bridge node\n");
return;
}
bus_range = of_get_property(pcictrl, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING EFIKA_PLATFORM_NAME
": Can't get bus-range for %s\n", pcictrl->full_name);
return;
}
if (bus_range[1] == bus_range[0])
printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI bus %d",
bus_range[0]);
else
printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI buses %d..%d",
bus_range[0], bus_range[1]);
printk(" controlled by %s\n", pcictrl->full_name);
printk("\n");
hose = pcibios_alloc_controller();
if (!hose) {
printk(KERN_WARNING EFIKA_PLATFORM_NAME
": Can't allocate PCI controller structure for %s\n",
pcictrl->full_name);
return;
}
hose->arch_data = of_node_get(pcictrl);
hose->first_busno = bus_range[0];
hose->last_busno = bus_range[1];
hose->ops = &rtas_pci_ops;
pci_process_bridge_OF_ranges(hose, pcictrl, 0);
}
static int __init amigaone_add_bridge(struct device_node *dev)
{
const u32 *cfg_addr, *cfg_data;
int len;
const int *bus_range;
struct pci_controller *hose;
printk(KERN_INFO "Adding PCI host bridge %s\n", dev->full_name);
cfg_addr = of_get_address(dev, 0, NULL, NULL);
cfg_data = of_get_address(dev, 1, NULL, NULL);
if ((cfg_addr == NULL) || (cfg_data == NULL))
return -ENODEV;
bus_range = of_get_property(dev, "bus-range", &len);
if ((bus_range == NULL) || (len < 2 * sizeof(int)))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
hose = pcibios_alloc_controller(dev);
if (hose == NULL)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, cfg_addr[0], cfg_data[0], 0);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, 1);
return 0;
}
static int __init linkstation_add_bridge(struct device_node *dev)
{
#ifdef CONFIG_PCI
int len;
struct pci_controller *hose;
const int *bus_range;
printk("Adding PCI host bridge %s\n", dev->full_name);
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
hose = pcibios_alloc_controller(dev);
if (hose == NULL)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, 1);
#endif
return 0;
}
static int of_pci_phb_probe(struct platform_device *dev)
{
struct pci_controller *phb;
/* Check if we can do that ... */
if (ppc_md.pci_setup_phb == NULL)
return -ENODEV;
pr_info("Setting up PCI bus %s\n", dev->dev.of_node->full_name);
/* Alloc and setup PHB data structure */
phb = pcibios_alloc_controller(dev->dev.of_node);
if (!phb)
return -ENODEV;
/* Setup parent in sysfs */
phb->parent = &dev->dev;
/* Setup the PHB using arch provided callback */
if (ppc_md.pci_setup_phb(phb)) {
pcibios_free_controller(phb);
return -ENODEV;
}
/* Process "ranges" property */
pci_process_bridge_OF_ranges(phb, dev->dev.of_node, 0);
/* Init pci_dn data structures */
pci_devs_phb_init_dynamic(phb);
/* Create EEH devices for the PHB */
eeh_dev_phb_init_dynamic(phb);
/* Register devices with EEH */
if (dev->dev.of_node->child)
eeh_add_device_tree_early(dev->dev.of_node);
/* Scan the bus */
pcibios_scan_phb(phb);
if (phb->bus == NULL)
return -ENXIO;
/* Claim resources. This might need some rework as well depending
* whether we are doing probe-only or not, like assigning unassigned
* resources etc...
*/
pcibios_claim_one_bus(phb->bus);
/* Finish EEH setup */
eeh_add_device_tree_late(phb->bus);
/* Add probed PCI devices to the device model */
pci_bus_add_devices(phb->bus);
/* sysfs files should only be added after devices are added */
eeh_add_sysfs_files(phb->bus);
return 0;
}
int __init add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 1, has_address = 0;
phys_addr_t immr = get_immrbase();
DBG("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
hose = pcibios_alloc_controller();
if (!hose)
return -ENOMEM;
hose->arch_data = dev;
hose->set_cfg_type = 1;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
/* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
* the other at 0x8600, we consider the 0x8500 the primary controller
*/
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
primary = 0;
hose->bus_offset = hose->first_busno;
mpc83xx_pci2_busno = hose->first_busno;
}
printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
static void __init
yucca_setup_hoses(void)
{
struct pci_controller *hose;
char name[20];
int i;
if (0 && ppc440spe_init_pcie()) {
printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
return;
}
for (i = 0; i <= 2; ++i) {
if (!yucca_pcie_card_present(i))
continue;
printk(KERN_INFO "PCIE%d: card present\n", i);
yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) {
printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
continue;
}
hose = pcibios_alloc_controller();
if (!hose)
return;
sprintf(name, "PCIE%d host bridge", i);
pci_init_resource(&hose->io_resource,
YUCCA_PCIX_LOWER_IO,
YUCCA_PCIX_UPPER_IO,
IORESOURCE_IO,
name);
hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
i * YUCCA_PCIE_MEM_SIZE;
hose->mem_space.end = hose->mem_space.start +
YUCCA_PCIE_MEM_SIZE - 1;
pci_init_resource(&hose->mem_resources[0],
hose->mem_space.start,
hose->mem_space.end,
IORESOURCE_MEM,
name);
hose->first_busno = 0;
hose->last_busno = 15;
hose_type[hose->index] = HOSE_PCIE0 + i;
ppc440spe_setup_pcie(hose, i);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
}
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = yucca_map_irq;
}
static void __init
luan_setup_hoses(void)
{
struct pci_controller *hose1, *hose2;
/* Configure windows on the PCI-X host bridge */
luan_setup_pcix();
/* Allocate hoses for PCIX1 and PCIX2 */
hose1 = pcibios_alloc_controller();
hose2 = pcibios_alloc_controller();
if (!hose1 || !hose2)
return;
/* Setup PCIX1 */
hose1->first_busno = 0;
hose1->last_busno = 0xff;
luan_setup_hose(hose1,
LUAN_PCIX1_LOWER_MEM,
LUAN_PCIX1_UPPER_MEM,
PCIX1_CFGA,
PCIX1_CFGD,
PCIX1_IO_BASE);
hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
/* Setup PCIX2 */
hose2->first_busno = hose1->last_busno + 1;
hose2->last_busno = 0xff;
luan_setup_hose(hose2,
LUAN_PCIX2_LOWER_MEM,
LUAN_PCIX2_UPPER_MEM,
PCIX2_CFGA,
PCIX2_CFGD,
PCIX2_IO_BASE);
hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = luan_map_irq;
}
/* The "bootloader" for Synergy boards does none of this for us, so we need to
lay it all out ourselves... --Dan */
void __init gemini_find_bridges(void)
{
struct pci_controller* hose;
ppc_md.pcibios_fixup = gemini_pcibios_fixup;
hose = pcibios_alloc_controller();
if (!hose)
return;
setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
}
static void __init
p3p440_setup_hose(void)
{
struct pci_controller *hose;
if (!is_monarch()) {
/*
* REMARK: This Non-Monarch mode need perhaps some changes.
* It's not tested at all, because of lack of hardware. --sr
*/
printk("P3P440-PCI: Non-Monarch detected, skipping PCI init!\n");
return;
}
/* Configure windows on the PCI-X host bridge */
p3p440_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = P3P440_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
P3P440_PCI_LOWER_IO,
P3P440_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
P3P440_PCI_LOWER_MEM,
P3P440_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = P3P440_PCI_LOWER_IO;
hose->io_space.end = P3P440_PCI_UPPER_IO;
hose->mem_space.start = P3P440_PCI_LOWER_MEM;
hose->mem_space.end = P3P440_PCI_UPPER_MEM;
hose->io_base_virt = ioremap64(P3P440_PCI_IO_BASE, P3P440_PCI_IO_SIZE);
isa_io_base = (unsigned long)hose->io_base_virt;
setup_indirect_pci(hose, PCIX0_CFGA, PCIX0_CFGD);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = p3p440_map_irq;
}
/**
* xilinx_pci_init - Find and register a Xilinx PCI host bridge
*/
void __init xilinx_pci_init(void)
{
struct pci_controller *hose;
struct resource r;
void __iomem *pci_reg;
struct device_node *pci_node;
pci_node = of_find_matching_node(NULL, xilinx_pci_match);
if(!pci_node)
return;
if (of_address_to_resource(pci_node, 0, &r)) {
pr_err("xilinx-pci: cannot resolve base address\n");
return;
}
hose = pcibios_alloc_controller(pci_node);
if (!hose) {
pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
return;
}
/* Setup config space */
setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
r.start + XPLB_PCI_DATA,
PPC_INDIRECT_TYPE_SET_CFG_TYPE);
/* According to the xilinx plbv46_pci documentation the soft-core starts
* a self-init when the bus master enable bit is set. Without this bit
* set the pci bus can't be scanned.
*/
early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
/* Set the max latency timer to 255 */
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
/* Set the max bus number to 255 */
pci_reg = of_iomap(pci_node, 0);
out_8(pci_reg + XPLB_PCI_BUS, 0xff);
iounmap(pci_reg);
/* Nothing past the root bridge is working right now. By default
* exclude config access to anything except bus 0 */
if (!ppc_md.pci_exclude_device)
ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
/* Register the host bridge with the linux kernel! */
pci_process_bridge_OF_ranges(hose, pci_node, 1);
pr_info("xilinx-pci: Registered PCI host bridge\n");
}
static void __init cell_add_phb(struct device_node *node, int index)
{
struct pci_controller *phb;
struct resource r;
phb = pcibios_alloc_controller(node);
if (!phb)
return;
setup_phb(node, phb);
if (of_address_to_resource(node, 0, &r) == 0)
phb->buid = r.start;
pci_process_bridge_OF_ranges(phb, node, 0);
pci_setup_phb_io(phb, index == 0);
}
int cxl_pci_vphb_add(struct cxl_afu *afu)
{
struct pci_dev *phys_dev;
struct pci_controller *phb, *phys_phb;
struct device_node *vphb_dn;
struct device *parent;
if (cpu_has_feature(CPU_FTR_HVMODE)) {
phys_dev = to_pci_dev(afu->adapter->dev.parent);
phys_phb = pci_bus_to_host(phys_dev->bus);
vphb_dn = phys_phb->dn;
parent = &phys_dev->dev;
} else {
vphb_dn = afu->adapter->dev.parent->of_node;
parent = afu->adapter->dev.parent;
}
/* Alloc and setup PHB data structure */
phb = pcibios_alloc_controller(vphb_dn);
if (!phb)
return -ENODEV;
/* Setup parent in sysfs */
phb->parent = parent;
/* Setup the PHB using arch provided callback */
phb->ops = &cxl_pcie_pci_ops;
phb->cfg_addr = NULL;
phb->cfg_data = 0;
phb->private_data = afu;
phb->controller_ops = cxl_pci_controller_ops;
/* Scan the bus */
pcibios_scan_phb(phb);
if (phb->bus == NULL)
return -ENXIO;
/* Claim resources. This might need some rework as well depending
* whether we are doing probe-only or not, like assigning unassigned
* resources etc...
*/
pcibios_claim_one_bus(phb->bus);
/* Add probed PCI devices to the device model */
pci_bus_add_devices(phb->bus);
afu->phb = phb;
return 0;
}
static void __init taiga_setup_bridge(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (hose){
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = TAIGA_PCI_MEM_OFFSET;
/* Setup resources to match map
* PCI memory and IO space are set in PFAB_BARs by boot code
* 64KB take one 16MB LUT entry, PFAB_IO
*/
pci_init_resource(&hose->io_resource, TAIGA_PCI_IO_START,
TAIGA_PCI_IO_END, IORESOURCE_IO,
"PCI host bridge");
/* OCN to PCI/X transaction is unchanged,
* bar1 first 8 LUTs, 128MB
*/
pci_init_resource(&hose->mem_resources[0],
TAIGA_PCI_MEM_START,
TAIGA_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
(hose)->io_space.start = TAIGA_PCI_IO_START;
(hose)->io_space.end = TAIGA_PCI_IO_END;
(hose)->mem_space.start = TAIGA_PCI_MEM_START;
(hose)->mem_space.end = TAIGA_PCI_MEM_END;
(hose)->io_base_virt = (void *)TAIGA_ISA_IO_BASE;
(hose)->ops = &direct_pci_ops;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = taiga_map_irq;
if (ppc_md.progress)
ppc_md.progress("tsi108: resources set", 0x100);
tsi108_bridge_init(hose, TSI108_CSR_ADDR_PHYS);
} else {
printk("PCI Host bridge init failed\n");
}
}
void __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
struct device_node *root = of_find_node_by_path("/");
for_each_child_of_node(root, node) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
isa_bridge_find_early(phb);
}
of_node_put(root);
pci_devs_phb_init();
/* Create EEH devices for all PHBs */
eeh_dev_phb_init();
/*
* PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = of_get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop) {
if (*prop)
pci_add_flags(PCI_PROBE_ONLY);
else
pci_clear_flags(PCI_PROBE_ONLY);
}
#ifdef CONFIG_PPC32 /* Will be made generic soon */
prop = of_get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop && *prop)
pci_add_flags(PCI_REASSIGN_ALL_BUS);
#endif /* CONFIG_PPC32 */
}
}
void __init
apus_setup_pci_ptrs(void)
{
if (!powerup_PCI_present) {
DPRINTK("no PCI bridge detected\n");
return;
}
DPRINTK("Phase5 B/CVisionPPC PCI bridge detected.\n");
apus_hose = pcibios_alloc_controller();
if (!apus_hose) {
printk("apus_pci: Can't allocate PCI controller structure\n");
return;
}
if (!(apus_hose->cfg_data = ioremap(CVPPC_PCI_CONFIG, 256))) {
printk("apus_pci: unable to map PCI config region\n");
return;
}
if (!(apus_hose->cfg_addr = ioremap(CSPPC_PCI_BRIDGE, 256))) {
printk("apus_pci: unable to map PCI bridge\n");
return;
}
writel(CSPPCF_BRIDGE_BIG_ENDIAN, apus_hose->cfg_addr + CSPPC_BRIDGE_ENDIAN);
DEFW();
writel(CVPPC_REGS_REGION, apus_hose->cfg_data+ PCI_BASE_ADDRESS_0);
DEFW();
writel(CVPPC_FB_APERTURE_ONE, apus_hose->cfg_data + PCI_BASE_ADDRESS_1);
DEFW();
writel(CVPPC_FB_APERTURE_TWO, apus_hose->cfg_data + PCI_BASE_ADDRESS_2);
DEFW();
writel(CVPPC_ROM_ADDRESS, apus_hose->cfg_data + PCI_ROM_ADDRESS);
DEFW();
writel(0xef000000 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER, apus_hose->cfg_data + PCI_COMMAND);
DEFW();
apus_hose->first_busno = 0;
apus_hose->last_busno = 0;
apus_hose->ops = &apus_pci_ops;
ppc_md.pcibios_fixup = apus_pcibios_fixup;
ppc_md.pcibios_fixup_bus = apus_pcibios_fixup_bus;
return;
}
static void __init
ebony_setup_hose(void)
{
struct pci_controller *hose;
/* Configure windows on the PCI-X host bridge */
ebony_setup_pcix();
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
EBONY_PCI_LOWER_IO,
EBONY_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
EBONY_PCI_LOWER_MEM,
EBONY_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = EBONY_PCI_LOWER_IO;
hose->io_space.end = EBONY_PCI_UPPER_IO;
hose->mem_space.start = EBONY_PCI_LOWER_MEM;
hose->mem_space.end = EBONY_PCI_UPPER_MEM;
isa_io_base =
(unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
hose->io_base_virt = (void *)isa_io_base;
setup_indirect_pci(hose,
EBONY_PCI_CFGA_PLB32,
EBONY_PCI_CFGD_PLB32);
hose->set_cfg_type = 1;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ebony_map_irq;
}
unsigned long __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
unsigned int index;
struct device_node *root = of_find_node_by_path("/");
index = 0;
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
pci_setup_phb_io(phb, index == 0);
index++;
}
of_node_put(root);
pci_devs_phb_init();
/*
* pci_probe_only and pci_assign_all_buses can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop)
pci_probe_only = *prop;
prop = get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop)
pci_assign_all_buses = *prop;
}
return 0;
}
void __init add_bridge(struct device_node *np)
{
int len;
struct pci_controller *hose;
struct resource r;
const int *bus_range;
const uint *ptr;
memset(&r, 0, sizeof(r));
if (of_address_to_resource(np, 0, &r)) {
printk(KERN_INFO "No PCI reg property in device tree\n");
return;
}
if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
printk(KERN_INFO "No clock-frequency property in PCI node");
return;
}
pci_clk_frq = *ptr;
of_node_put(np);
bus_range = of_get_property(np, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", np->full_name);
}
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->arch_data = np;
hose->set_cfg_type = 1;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
hose->bus_offset = 0;
hose->set_cfg_type = 1;
setup_indirect_pci(hose,
r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
r.start + offsetof(pci_cpm2_t, pci_cfg_data));
pci_process_bridge_OF_ranges(hose, np, 1);
}
int __init tsi108_setup_pci(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 0, has_address = 0;
/* PCI Config mapping */
tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
TSI108_PCI_CFG_SIZE);
DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
tsi108_pci_cfg_base);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
hose = pcibios_alloc_controller();
if (!hose) {
printk("PCI Host bridge init failed\n");
return -ENOMEM;
}
hose->arch_data = dev;
hose->set_cfg_type = 1;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
(hose)->ops = &tsi108_direct_pci_ops;
printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
"Firmware bus number: %d->%d\n",
rsrc.start, hose->first_busno, hose->last_busno);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
static int __init mv64x60_add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary;
memset(&rsrc, 0, sizeof(rsrc));
/* Fetch host bridge registers address */
if (of_address_to_resource(dev, 0, &rsrc)) {
printk(KERN_ERR "No PCI reg property in device tree\n");
return -ENODEV;
}
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->set_cfg_type = 1;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
hose->bus_offset = hose->first_busno;
printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
primary = (hose->first_busno == 0);
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
void __init
galaxy_find_bridges(void)
{
struct pci_controller* hose;
set_config_access_method(galaxy);
ppc_md.pcibios_fixup = galaxy_pcibios_fixup;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->ops = &galaxy_pci_ops;
/* Todo ...
hose->cfg_data = ioremap(PCICFGDATA, ...);
hose->cfg_addr = ioremap(PCICFGADDR, ...);
*/
}
void __init platform_pcibios_init(void)
{
struct pci_controller *pci_ctrl;
/* Setup pci_controller */
pci_ctrl = pcibios_alloc_controller();
if (!pci_ctrl) {
printk("PCI: cannot allocate space for the pci controller\n");
return;
}
/* Move V3USC to 0xFD000000 */
V3USC_LB_REG_BASE_W = PCI_V320_BASE >> 16;
*(unsigned int*)(XT2000_V3CFG_PADDR) = 0;
/* Initialize the V3 */
v320usc_pci_init();
/* Setup the controller */
pci_ctrl->first_busno = 0;
pci_ctrl->last_busno = 0xff;
pci_ctrl->ops = &v320usc_pci_ops;
pci_ctrl->map_irq = map_irq;
pci_ctrl->io_space.start = PCI_IO_SPACE_PCI_BASE;
pci_ctrl->io_space.end = PCI_IO_SPACE_PCI_BASE + PCI_IO_SPACE_SIZE;
pci_ctrl->io_space.base = PCI_IO_SPACE_CPU_BASE;
pci_ctrl->mem_space.start = PCI_MEM_SPACE_PCI_BASE;
pci_ctrl->mem_space.end = PCI_MEM_SPACE_PCI_BASE + PCI_MEM_SPACE_SIZE;
pci_ctrl->mem_space.base = 0;
pcibios_init_resource(&pci_ctrl->io_resource,
PCI_IO_SPACE_PCI_BASE,
PCI_IO_SPACE_PCI_BASE + PCI_IO_SPACE_SIZE,
IORESOURCE_IO, "PCI host bridge");
pcibios_init_resource(&pci_ctrl->mem_resources[0],
PCI_MEM_SPACE_CPU_BASE,
PCI_MEM_SPACE_CPU_BASE + PCI_MEM_SPACE_SIZE,
IORESOURCE_MEM, "PCI host bridge");
/* Enumerate the PCI bus */
pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno);
}
int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int has_address = 0;
tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
tsi108_pci_cfg_phys = cfg_phys;
DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
tsi108_pci_cfg_base);
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
hose = pcibios_alloc_controller(dev);
if (!hose) {
printk("PCI Host bridge init failed\n");
return -ENOMEM;
}
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
(hose)->ops = &tsi108_direct_pci_ops;
printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
"Firmware bus number: %d->%d\n",
rsrc.start, hose->first_busno, hose->last_busno);
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
void __init find_and_init_phbs(void)
{
struct device_node *node;
struct pci_controller *phb;
struct device_node *root = of_find_node_by_path("/");
for (node = of_get_next_child(root, NULL);
node != NULL;
node = of_get_next_child(root, node)) {
if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
strcmp(node->type, "pciex") != 0))
continue;
phb = pcibios_alloc_controller(node);
if (!phb)
continue;
rtas_setup_phb(phb);
pci_process_bridge_OF_ranges(phb, node, 0);
isa_bridge_find_early(phb);
}
of_node_put(root);
pci_devs_phb_init();
/*
* pci_probe_only and pci_assign_all_buses can be set via properties
* in chosen.
*/
if (of_chosen) {
const int *prop;
prop = of_get_property(of_chosen,
"linux,pci-probe-only", NULL);
if (prop)
pci_probe_only = *prop;
#ifdef CONFIG_PPC32 /* Will be made generic soon */
prop = of_get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop && *prop)
ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
#endif /* CONFIG_PPC32 */
}
}
void __init
mvme5100_setup_bridge(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
MVME5100_PCI_LOWER_IO,
MVME5100_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
MVME5100_PCI_LOWER_MEM,
MVME5100_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = MVME5100_PCI_LOWER_IO;
hose->io_space.end = MVME5100_PCI_UPPER_IO;
hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
/* Use indirect method of Hawk */
setup_indirect_pci(hose,
MVME5100_PCI_CONFIG_ADDR,
MVME5100_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = mvme5100_map_irq;
}
void __init prpmc750_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET;
pci_init_resource(&hose->io_resource,
PRPMC750_PCI_IO_START,
PRPMC750_PCI_IO_END,
IORESOURCE_IO, "PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END,
IORESOURCE_MEM, "PCI host bridge");
hose->io_space.start = PRPMC750_PCI_IO_START;
hose->io_space.end = PRPMC750_PCI_IO_END;
hose->mem_space.start = PRPMC750_PCI_MEM_START;
hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE;
if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE,
PRPMC750_PROC_PCI_MEM_START,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END,
PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
!= 0) {
printk(KERN_CRIT "Could not initialize host bridge\n");
}
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}