/*
* Return TRUE if PME status set
*/
bool
pcicore_pmestat(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
uint32 w;
if (!pcicore_pmecap(pi))
return FALSE;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
}
/* Enable PME generation */
void
pcicore_pmeen(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
uint32 w;
/* if not pmecapable return */
if (!pcicore_pmecap(pi))
return;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
w |= (PME_CSR_PME_EN);
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32), w);
}
/* Disable PME generation, clear the PME status bit if set
*/
void
pcicore_pmeclr(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
uint32 w;
if (!pcicore_pmecap(pi))
return;
pcie_war_pmebits(pi);
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
/* PMESTAT is cleared by writing 1 to it */
w &= ~(PME_CSR_PME_EN);
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32), w);
}
void
pcicore_pmestatclr(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
uint32 w;
if (!pcicore_pmecap(pi))
return;
pcie_war_pmebits(pi);
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
PCI_ERROR(("pcicore_pmestatclr PMECSR : 0x%x\n", w));
/* Writing a 1 to PMESTAT will clear it */
if ((w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT) {
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32),
w);
}
}
/* Disable PME generation, clear the PME status bit if set and
* return TRUE if PME status set
*/
bool
pcicore_pmeclr(void *pch)
{
pcicore_info_t *pi = (pcicore_info_t *)pch;
uint32 w;
bool ret = FALSE;
if (!pcicore_pmecap(pi))
return ret;
w = OSL_PCI_READ_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32));
PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
ret = (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
/* PMESTAT is cleared by writing 1 to it */
w &= ~(PME_CSR_PME_EN);
OSL_PCI_WRITE_CONFIG(pi->osh, pi->pmecap_offset + PME_CSR_OFFSET, sizeof(uint32), w);
return ret;
}