/**
* \brief The callback function for PDCA channel of PARC
*
* \param status PDCA channel status
*/
static void pdca_parc_callback(enum pdca_channel_status status)
{
UNUSED(status);
printf("End of capture.\r\n");
for (uint32_t uc_i = 0; uc_i < BUFFER_SIZE; uc_i++) {
printf("0x%02X ", gs_puc_buffer[uc_i]);
}
printf("\r\n");
/* disable interrupt for pdca channel of PARC*/
pdca_channel_disable_interrupt(PDCA_PARC_CHANNEL,PDCA_IER_RCZ);
pdca_channel_disable(PDCA_PARC_CHANNEL);
puts("\n\rThe example is done!\n\r");
}
/**
* \brief Test ECB mode encryption and decryption with PDCA.
*
* \param test Current test case.
*/
static void run_ecb_mode_test_pdca(const struct test_case *test)
{
/* Change the AES interrupt callback function. */
aes_set_callback(&g_aes_inst, AES_INTERRUPT_INPUT_BUFFER_READY,
aes_callback_pdca, 1);
/* Enable PDCA module clock */
pdca_enable(PDCA);
state = false;
/* Configure the AES. */
g_aes_inst.aes_cfg->encrypt_mode = AES_ENCRYPTION;
g_aes_inst.aes_cfg->key_size = AES_KEY_SIZE_128;
g_aes_inst.aes_cfg->dma_mode = AES_DMA_MODE;
g_aes_inst.aes_cfg->opmode = AES_ECB_MODE;
g_aes_inst.aes_cfg->cfb_size = AES_CFB_SIZE_128;
g_aes_inst.aes_cfg->countermeasure_mask = AES_COUNTERMEASURE_TYPE_ALL;
aes_set_config(&g_aes_inst);
/* Beginning of a new message. */
aes_set_new_message(&g_aes_inst);
/* Set the cryptographic key. */
aes_write_key(&g_aes_inst, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be ciphered to the input data registers. */
/* Init PDCA channel with the pdca_options.*/
PDCA_TX_OPTIONS.addr = (void *)ref_plain_text; /* memory address */
PDCA_TX_OPTIONS.pid = AESA_PDCA_ID_TX; /* select peripheral - AESA TX.*/
PDCA_TX_OPTIONS.size = AES_EXAMPLE_REFBUF_SIZE; /* transfer counter */
PDCA_TX_OPTIONS.r_addr = (void *)0; /* next memory address */
PDCA_TX_OPTIONS.r_size = 0; /* next transfer counter */
PDCA_TX_OPTIONS.transfer_size = PDCA_MR_SIZE_WORD;
pdca_channel_set_config(PDCA_TX_CHANNEL, &PDCA_TX_OPTIONS);
PDCA_RX_OPTIONS.addr = (void *)output_data; /* memory address */
PDCA_RX_OPTIONS.pid = AESA_PDCA_ID_RX; /* select peripheral - AESA RX.*/
PDCA_RX_OPTIONS.size = AES_EXAMPLE_REFBUF_SIZE; /* transfer counter */
PDCA_RX_OPTIONS.r_addr = (void *)0; /* next memory address */
PDCA_RX_OPTIONS.r_size = 0; /* next transfer counter */
PDCA_RX_OPTIONS.transfer_size = PDCA_MR_SIZE_WORD;
pdca_channel_set_config(PDCA_RX_CHANNEL, &PDCA_RX_OPTIONS);
/* Enable PDCA channel, start transfer data. */
pdca_channel_enable(PDCA_TX_CHANNEL);
/* Wait for the end of the encryption process. */
delay_ms(30);
/* Disable PDCA channel. */
pdca_channel_disable(PDCA_RX_CHANNEL);
pdca_channel_disable(PDCA_TX_CHANNEL);
if ((ref_cipher_text_ecb[0] != output_data[0]) ||
(ref_cipher_text_ecb[1] != output_data[1]) ||
(ref_cipher_text_ecb[2] != output_data[2]) ||
(ref_cipher_text_ecb[3] != output_data[3])) {
flag = false;
} else {
flag = true;
}
test_assert_true(test, flag == true, "ECB mode encryption not work!");
state = false;
/* Configure the AES. */
g_aes_inst.aes_cfg->encrypt_mode = AES_DECRYPTION;
g_aes_inst.aes_cfg->key_size = AES_KEY_SIZE_128;
g_aes_inst.aes_cfg->dma_mode = AES_DMA_MODE;
g_aes_inst.aes_cfg->opmode = AES_ECB_MODE;
g_aes_inst.aes_cfg->cfb_size = AES_CFB_SIZE_128;
g_aes_inst.aes_cfg->countermeasure_mask = AES_COUNTERMEASURE_TYPE_ALL;
aes_set_config(&g_aes_inst);
/* Beginning of a new message. */
aes_set_new_message(&g_aes_inst);
/* Set the cryptographic key. */
aes_write_key(&g_aes_inst, key128);
/* The initialization vector is not used by the ECB cipher mode. */
/* Write the data to be deciphered to the input data registers. */
/* Init PDCA channel with the pdca_options.*/
PDCA_TX_OPTIONS.addr = (void *)ref_cipher_text_ecb; /* memory address */
PDCA_TX_OPTIONS.pid = AESA_PDCA_ID_TX; /* select peripheral - AESA TX.*/
PDCA_TX_OPTIONS.size = AES_EXAMPLE_REFBUF_SIZE; /* transfer counter */
PDCA_TX_OPTIONS.r_addr = (void *)0; /* next memory address */
PDCA_TX_OPTIONS.r_size = 0; /* next transfer counter */
PDCA_TX_OPTIONS.transfer_size = PDCA_MR_SIZE_WORD;
pdca_channel_set_config(PDCA_TX_CHANNEL, &PDCA_TX_OPTIONS);
PDCA_RX_OPTIONS.addr = (void *)output_data; /* memory address */
PDCA_RX_OPTIONS.pid = AESA_PDCA_ID_RX; /* select peripheral - AESA RX.*/
PDCA_RX_OPTIONS.size = AES_EXAMPLE_REFBUF_SIZE; /* transfer counter */
PDCA_RX_OPTIONS.r_addr = (void *)0; /* next memory address */
PDCA_RX_OPTIONS.r_size = 0; /* next transfer counter */
PDCA_RX_OPTIONS.transfer_size = PDCA_MR_SIZE_WORD;
pdca_channel_set_config(PDCA_RX_CHANNEL, &PDCA_RX_OPTIONS);
/* Enable PDCA channel, start transfer data. */
pdca_channel_enable(PDCA_TX_CHANNEL);
/* Wait for the end of the decryption process. */
delay_ms(30);
/* Disable PDCA channel. */
pdca_channel_disable(PDCA_RX_CHANNEL);
pdca_channel_disable(PDCA_TX_CHANNEL);
/* check the result. */
if ((ref_plain_text[0] != output_data[0]) ||
(ref_plain_text[1] != output_data[1]) ||
(ref_plain_text[2] != output_data[2]) ||
(ref_plain_text[3] != output_data[3])) {
flag = false;
} else {
flag = true;
}
test_assert_true(test, flag == true, "ECB mode decryption not work!");
/* Disable PDCA module clock */
pdca_disable(PDCA);
/* Change back the AES interrupt callback function. */
aes_set_callback(&g_aes_inst, AES_INTERRUPT_INPUT_BUFFER_READY,
aes_callback, 1);
}
/**
* \brief Test audio data transfer and receive.
*
* \param test Current test case.
*/
static void run_iis_test(const struct test_case *test)
{
uint32_t i;
struct iis_config config;
struct iis_dev_inst dev_inst;
struct genclk_config gencfg;
struct pll_config pcfg;
/* Set the GCLK according to the sample rate */
genclk_config_defaults(&gencfg, IISC_GCLK_NUM);
/* CPUCLK 48M */
pll_config_init(&pcfg, PLL_SRC_OSC0, 2, 96000000 /
BOARD_OSC0_HZ);
pll_enable(&pcfg, 0);
sysclk_set_prescalers(0, 0, 0, 0, 0);
pll_wait_for_lock(0);
sysclk_set_source(SYSCLK_SRC_PLL0);
/* GCLK according fs ratio */
genclk_enable_source(GENCLK_SRC_CLK_CPU);
genclk_config_set_source(&gencfg, GENCLK_SRC_CLK_CPU);
genclk_config_set_divider(&gencfg, 4);
genclk_enable(&gencfg, IISC_GCLK_NUM);
/* Set the configuration */
iis_get_config_defaults(&config);
config.data_format = IIS_DATE_16BIT_COMPACT;
config.slot_length = IIS_SLOT_LENGTH_16BIT;
config.fs_ratio = IIS_FS_RATE_256;
config.tx_channels = IIS_CHANNEL_STEREO;
config.rx_channels = IIS_CHANNEL_STEREO;
config.tx_dma = IIS_ONE_DMA_CHANNEL_FOR_BOTH_CHANNELS;
config.rx_dma = IIS_ONE_DMA_CHANNEL_FOR_BOTH_CHANNELS;
config.loopback = true;
iis_init(&dev_inst, IISC, &config);
/* Enable the IIS module. */
iis_enable(&dev_inst);
/* Config PDCA module */
pdca_enable(PDCA);
pdca_channel_set_config(PDCA_IISC_CHANNEL0, &pdca_iisc_config_tx);
pdca_channel_set_config(PDCA_IISC_CHANNEL1, &pdca_iisc_config_rx);
pdca_channel_write_load(PDCA_IISC_CHANNEL0,
(void *)output_samples, SOUND_SAMPLES / 2);
pdca_channel_write_load(PDCA_IISC_CHANNEL1,
(void *)input_samples, SOUND_SAMPLES / 2);
pdca_channel_enable(PDCA_IISC_CHANNEL0);
pdca_channel_enable(PDCA_IISC_CHANNEL1);
/* Enable the functions */
iis_enable_transmission(&dev_inst);
iis_enable_clocks(&dev_inst);
/**
* Since the transfer and receive timing is not under control, we
* need adjust here the enable sequence and add some delay
* functions if it's needed.
*/
delay_us(20);
iis_enable_reception(&dev_inst);
while (!(pdca_get_channel_status(PDCA_IISC_CHANNEL1)
== PDCA_CH_TRANSFER_COMPLETED)) {
}
/* Disable the PDCA module. */
pdca_channel_disable(PDCA_IISC_CHANNEL0);
pdca_channel_disable(PDCA_IISC_CHANNEL1);
pdca_disable(PDCA);
/* Disable the IISC module. */
iis_disable(&dev_inst);
for (i = 0; i < SOUND_SAMPLES; i++) {
if (input_samples[i] != output_samples[i]) {
flag = false;
}
}
test_assert_true(test, flag == true, "Audio data did not match!");
}
