/* * First C code run on the secondary CPUs after being started up by * the master. */ asmlinkage __cpuinit void start_secondary(void) { unsigned int cpu; #ifdef CONFIG_MIPS_MT_SMTC /* Only do cpu_probe for first TC of CPU */ if ((read_c0_tcbind() & TCBIND_CURTC) == 0) #endif /* CONFIG_MIPS_MT_SMTC */ cpu_probe(); cpu_report(); per_cpu_trap_init(); prom_init_secondary(); /* * XXX parity protection should be folded in here when it's converted * to an option instead of something based on .cputype */ calibrate_delay(); preempt_disable(); cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; prom_smp_finish(); cpu_set(cpu, cpu_callin_map); cpu_idle(); }
asmlinkage void start_secondary(void) { unsigned int cpu = smp_processor_id(); struct mm_struct *mm = &init_mm; enable_mmu(); mmgrab(mm); mmget(mm); current->active_mm = mm; #ifdef CONFIG_MMU enter_lazy_tlb(mm, current); local_flush_tlb_all(); #endif per_cpu_trap_init(); preempt_disable(); notify_cpu_starting(cpu); local_irq_enable(); calibrate_delay(); smp_store_cpu_info(cpu); set_cpu_online(cpu, true); per_cpu(cpu_state, cpu) = CPU_ONLINE; cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); }
asmlinkage void start_secondary(void) { unsigned int cpu = smp_processor_id(); struct mm_struct *mm = &init_mm; enable_mmu(); atomic_inc(&mm->mm_count); atomic_inc(&mm->mm_users); current->active_mm = mm; enter_lazy_tlb(mm, current); local_flush_tlb_all(); per_cpu_trap_init(); preempt_disable(); notify_cpu_starting(cpu); local_irq_enable(); /* Enable local timers */ local_timer_setup(cpu); calibrate_delay(); smp_store_cpu_info(cpu); set_cpu_online(cpu, true); per_cpu(cpu_state, cpu) = CPU_ONLINE; cpu_startup_entry(CPUHP_ONLINE); }
/* * First C code run on the secondary CPUs after being started up by * the master. */ asmlinkage void start_secondary(void) { unsigned int cpu; cpu_probe(); cpu_report(); per_cpu_trap_init(); prom_init_secondary(); /* * XXX parity protection should be folded in here when it's converted * to an option instead of something based on .cputype */ #ifndef CONFIG_CPU_CAVIUM_OCTEON /* There is no reason to waste time doing this on Octeon. All the cores are on the same chip and are the same speed by definition */ calibrate_delay(); #endif preempt_disable(); cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; prom_smp_finish(); cpu_set(cpu, cpu_callin_map); cpu_idle(); }
asmlinkage void __cpuinit start_secondary(void) { unsigned int cpu; struct mm_struct *mm = &init_mm; atomic_inc(&mm->mm_count); atomic_inc(&mm->mm_users); current->active_mm = mm; BUG_ON(current->mm); enter_lazy_tlb(mm, current); per_cpu_trap_init(); preempt_disable(); local_irq_enable(); calibrate_delay(); cpu = smp_processor_id(); smp_store_cpu_info(cpu); cpu_set(cpu, cpu_online_map); cpu_idle(); }
/* * First C code run on the secondary CPUs after being started up by * the master. */ asmlinkage void start_secondary(void) { unsigned int cpu; cpu_probe(); cpu_report(); per_cpu_trap_init(); prom_init_secondary(); /* * XXX parity protection should be folded in here when it's converted * to an option instead of something based on .cputype */ calibrate_delay(); preempt_disable(); cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; prom_smp_finish(); cpu_set(cpu, cpu_callin_map); cpu_idle(); }
int start_secondary(void *unused) { unsigned int cpu; cpu = smp_processor_id(); atomic_inc(&init_mm.mm_count); current->active_mm = &init_mm; smp_store_cpu_info(cpu); __smp_slave_init(cpu); preempt_disable(); per_cpu_trap_init(); atomic_inc(&cpus_booted); cpu_idle(); return 0; }
/* * Hook for doing final board-specific setup after the generic smp setup * is done */ asmlinkage void start_secondary(void) { unsigned int cpu = smp_processor_id(); prom_init_secondary(); per_cpu_trap_init(); /* * XXX parity protection should be folded in here when it's converted * to an option instead of something based on .cputype */ pgd_current[cpu] = init_mm.pgd; cpu_data[cpu].udelay_val = loops_per_jiffy; prom_smp_finish(); printk("Slave cpu booted successfully\n"); CPUMASK_SETB(cpu_online_map, cpu); atomic_inc(&cpus_booted); while (!atomic_read(&smp_commenced)); cpu_idle(); }