int power_init_board(void) { struct pmic *p; unsigned int reg, ret; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; ret = pfuze_mode_init(p, APS_PFM); if (ret < 0) return ret; /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_2_80V; pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); /* Increase VGEN5 from 2.8 to 3V */ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_3_00V; pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); return 0; }
int power_init_board(void) { struct pmic *p; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; return 0; }
int power_init_board(void) { unsigned int reg, ret; pfuze = pfuze_common_init(I2C_PMIC); if (!pfuze) return -ENODEV; ret = pfuze_mode_init(pfuze, APS_PFM); if (ret < 0) return ret; /* Increase VGEN3 from 2.5 to 2.8V */ pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_2_80V; pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); /* Increase VGEN5 from 2.8 to 3V */ pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_3_00V; pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); /* set SW1AB staby volatage 0.975V*/ pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); reg &= ~0x3f; reg |= 0x1b; pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); reg &= ~0xc0; reg |= 0x40; pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); /* set SW1C staby volatage 0.975V*/ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); reg &= ~0x3f; reg |= 0x1b; pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); reg &= ~0xc0; reg |= 0x40; pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); return 0; }
int power_init_board(void) { unsigned int reg, ret; pfuze = pfuze_common_init(I2C_PMIC); if (!pfuze) return -ENODEV; ret = pfuze_mode_init(pfuze, APS_PFM); if (ret < 0) return ret; /* set SW1AB standby volatage 0.975V */ pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); reg &= ~0x3f; reg |= PFUZE100_SW1ABC_SETP(9750); pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); reg &= ~0xc0; reg |= 0x40; pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); /* set SW1C standby volatage 1.10V */ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); reg &= ~0x3f; reg |= PFUZE100_SW1ABC_SETP(11000); pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); reg &= ~0xc0; reg |= 0x40; pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); /* Enable power of VGEN5 3V3, needed for SD3 */ pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; reg |= (LDOB_3_30V | (1 << LDO_EN)); pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); return 0; }
int power_init_board(void) { struct pmic *p; unsigned int value; p = pfuze_common_init(I2C_PMIC); if (!p) return -ENODEV; if (is_mx6dqp()) { /* set SW2 staby volatage 0.975V*/ pmic_reg_read(p, PFUZE100_SW2STBY, &value); value &= ~0x3f; value |= 0x17; pmic_reg_write(p, PFUZE100_SW2STBY, value); } return pfuze_mode_init(p, APS_PFM); }