static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data) { if (addr == 0xfe) { msleep(50); } else if (addr == 0xfd) { mdelay(5); } else if (addr == 0xfc) { mdelay(1); } else if (addr == 0xfb) { udelay(50); } else if (addr == 0xfa) { udelay(5); } else if (addr == 0xf9) { udelay(1); } else { phy_set_bb_reg(adapt, addr, bMaskDWord, data); /* Add 1us delay between BB/RF register setting. */ udelay(1); } }
void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV)) return; if (!dm_odm->bLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); if (dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } return; } else { if (!dm_fat_tbl->bBecomeLinked) { ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 1); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; } } if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) rtl88eu_dm_hw_ant_div(dm_odm); }
void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant) { struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct adapter *adapter = dm_odm->Adapter; u32 default_ant, optional_ant; if (dm_fat_tbl->RxIdleAnt != ant) { if (ant == MAIN_ANT) { default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; } else { default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; } if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, default_ant); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, optional_ant); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, default_ant); phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, default_ant); } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, default_ant); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, optional_ant); } } dm_fat_tbl->RxIdleAnt = ant; }
void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, u8 *powerlevel) { struct hal_data_8188e *hal_data = adapt->HalData; struct dm_priv *pdmpriv = &hal_data->dmpriv; struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; u32 tx_agc[2] = {0, 0}, tmpval = 0, pwrtrac_value; u8 idx1, idx2; u8 *ptr; u8 direction; if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { tx_agc[RF_PATH_A] = 0x3f3f3f3f; tx_agc[RF_PATH_B] = 0x3f3f3f3f; for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { tx_agc[idx1] = powerlevel[idx1] | (powerlevel[idx1]<<8) | (powerlevel[idx1]<<16) | (powerlevel[idx1]<<24); } } else { if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { tx_agc[RF_PATH_A] = 0x10101010; tx_agc[RF_PATH_B] = 0x10101010; } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { tx_agc[RF_PATH_A] = 0x00000000; tx_agc[RF_PATH_B] = 0x00000000; } else { for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { tx_agc[idx1] = powerlevel[idx1] | (powerlevel[idx1]<<8) | (powerlevel[idx1]<<16) | (powerlevel[idx1]<<24); } if (hal_data->EEPROMRegulatory == 0) { tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][6] + (hal_data->MCSTxPowerLevelOriginalOffset[0][7]<<8); tx_agc[RF_PATH_A] += tmpval; tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][14] + (hal_data->MCSTxPowerLevelOriginalOffset[0][15]<<24); tx_agc[RF_PATH_B] += tmpval; } } } for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { ptr = (u8 *)(&(tx_agc[idx1])); for (idx2 = 0; idx2 < 4; idx2++) { if (*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; ptr++; } } rtl88eu_dm_txpower_track_adjust(&hal_data->odmpriv, 1, &direction, &pwrtrac_value); if (direction == 1) { /* Increase TX power */ tx_agc[0] += pwrtrac_value; tx_agc[1] += pwrtrac_value; } else if (direction == 2) { /* Decrease TX power */ tx_agc[0] -= pwrtrac_value; tx_agc[1] -= pwrtrac_value; } /* rf-A cck tx power */ tmpval = tx_agc[RF_PATH_A]&0xff; phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); tmpval = tx_agc[RF_PATH_A]>>8; phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); /* rf-B cck tx power */ tmpval = tx_agc[RF_PATH_B]>>24; phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); tmpval = tx_agc[RF_PATH_B]&0x00ffffff; phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); }
static void dm_fast_training_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32, i; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; u32 AntCombination = 2; if (*(dm_odm->mp_mode) == 1) { return; } for (i = 0; i < 6; i++) { dm_fat_tbl->Bssid[i] = 0; dm_fat_tbl->antSumRSSI[i] = 0; dm_fat_tbl->antRSSIcnt[i] = 0; dm_fat_tbl->antAveRSSI[i] = 0; } dm_fat_tbl->TrainIdx = 0; dm_fat_tbl->FAT_State = FAT_NORMAL_STATE; /* MAC Setting */ value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord); phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord); phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Match MAC ADDR */ phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0); phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0); phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0); phy_set_bb_reg(adapter, 0x864, BIT10, 0); phy_set_bb_reg(adapter, 0xb2c, BIT22, 0); phy_set_bb_reg(adapter, 0xb2c, BIT31, 1); phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0); /* antenna mapping table */ if (AntCombination == 2) { if (!dm_odm->bIsMPChip) { /* testchip */ phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1); phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2); } else { /* MPchip */ phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1); phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2); } } else if (AntCombination == 7) { if (!dm_odm->bIsMPChip) { /* testchip */ phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0); phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1); phy_set_bb_reg(adapter, 0x878, BIT16, 0); phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2); phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3); phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4); phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5); phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6); phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7); } else { /* MPchip */ phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0); phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1); phy_set_bb_reg(adapter, 0x914, bMaskByte2, 2); phy_set_bb_reg(adapter, 0x914, bMaskByte3, 3); phy_set_bb_reg(adapter, 0x918, bMaskByte0, 4); phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5); phy_set_bb_reg(adapter, 0x918, bMaskByte2, 6); phy_set_bb_reg(adapter, 0x918, bMaskByte3, 7); } } /* Default Ant Setting when no fast training */ phy_set_bb_reg(adapter, 0x80c, BIT21, 1); phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0); phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); /* Enter Traing state */ phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); phy_set_bb_reg(adapter, 0xc50, BIT7, 1); }
static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); return; } /* MAC Setting */ value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Pin Settings */ phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* OFDM Settings */ phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* Tx Settings */ phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); /* antenna mapping table */ if (!dm_odm->bIsMPChip) { /* testchip */ phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1); phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2); } else { /* MPchip */ phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); } }
static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); return; } /* MAC Setting */ value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Pin Settings */ phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0); phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* OFDM Settings */ phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT); phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); }