static WRITE_HANDLER(gpsm_data_w)
{
// only four bits from mpu, upper ones are high
logerror("snd_data_w: %02x\n", data);
gps_locals.sndCmd = 0xf0 | (data & 0x0f);
pia_set_input_b(GPS_PIA0, gps_locals.sndCmd);
}
static WRITE_HANDLER(s67s_cmd_w) {
if (s67slocals.brdData.subType) { // don't use sound dips
data &= 0x7f;
} else {
data = (data & 0x1f) | (core_getDip(0)<<5);
}
pia_set_input_b(S67S_PIA0, data);
if (s67slocals.brdData.subType) {
pia_set_input_cb1(S67S_PIA0, !((data & 0x7f) == 0x7f));
} else {
pia_set_input_cb1(S67S_PIA0, !((data & 0x1f) == 0x1f));
}
}
static WRITE8_HANDLER( apple1_pia0_dsp_write_signal )
{
/* PIA output CB2 is inverted to become the DA signal, used to
signal a display write to the video hardware. */
/* DA is directly connected to PIA input PB7, so the processor can
read bit 7 of port B to test whether the display has completed
a write. */
pia_set_input_b(0, (!data) << 7);
/* Once DA is asserted, the display will wait until it can perform
the write, when the cursor position is about to be refreshed.
Only then will it assert \RDA to signal readiness for another
write. Thus the write delay depends on the cursor position and
where the display is in the refresh cycle. */
if (!data)
timer_set(apple1_vh_dsp_time_to_ready(), 0, apple1_dsp_ready_start);
}
void pia_8_portb_w (int offset, int data) { pia_set_input_b (7, data); }
void pia_7_portb_w (int offset, int data) { pia_set_input_b (6, data); }
void pia_6_portb_w (int offset, int data) { pia_set_input_b (5, data); }
void pia_5_portb_w (int offset, int data) { pia_set_input_b (4, data); }
void pia_4_portb_w (int offset, int data) { pia_set_input_b (3, data); }
void pia_3_portb_w (int offset, int data) { pia_set_input_b (2, data); }
void pia_2_portb_w (int offset, int data) { pia_set_input_b (1, data); }
void pia_1_portb_w (int offset, int data) { pia_set_input_b (0, data); }
