static int pil_lpass_reset(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
phys_addr_t start_addr = pil_get_entry_addr(pil);
int ret;
writel_relaxed(0, drv->restart_reg);
mb();
udelay(2);
ret = pil_lpass_enable_clks(drv);
if (ret)
return ret;
writel_relaxed((start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
ret = pil_q6v5_reset(pil);
if (ret) {
pil_lpass_disable_clks(drv);
return ret;
}
drv->is_booted = true;
return 0;
}
static int pil_lpass_reset(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
phys_addr_t start_addr = pil_get_entry_addr(pil);
int ret;
/* Deassert reset to subsystem and wait for propagation */
writel_relaxed(0, drv->restart_reg);
mb();
udelay(2);
ret = pil_lpass_enable_clks(drv);
if (ret)
return ret;
/* Program Image Address */
writel_relaxed((start_addr >> 4) & 0x0FFFFFF0,
drv->reg_base + QDSP6SS_RST_EVB);
ret = pil_q6v5_reset(pil);
if (ret) {
pil_lpass_disable_clks(drv);
return ret;
}
drv->is_booted = true;
return 0;
}
static int pil_lpass_shutdown(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
pil_q6v5_halt_axi_port(pil, drv->axi_halt_base);
if (drv->is_booted == false)
pil_lpass_enable_clks(drv);
pil_q6v5_shutdown(pil);
pil_lpass_disable_clks(drv);
writel_relaxed(1, drv->restart_reg);
drv->is_booted = false;
return 0;
}
static int pil_lpass_shutdown(struct pil_desc *pil)
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
pil_q6v5_halt_axi_port(pil, drv->axi_halt_base);
/*
* If the shutdown function is called before the reset function, clocks
* will not be enabled yet. Enable them here so that register writes
* performed during the shutdown succeed.
*/
if (drv->is_booted == false)
pil_lpass_enable_clks(drv);
pil_q6v5_shutdown(pil);
pil_lpass_disable_clks(drv);
writel_relaxed(1, drv->restart_reg);
drv->is_booted = false;
return 0;
}
