#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <hwconfig.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 2 },
{ pinmux(5), 1, 4 },
{ pinmux(5), 1, 5 }
};
/* UART pin muxer settings */
static const struct pinmux_config uart_pins[] = {
{ pinmux(0), 4, 6 },
{ pinmux(0), 4, 7 },
{ pinmux(4), 2, 4 },
{ pinmux(4), 2, 5 }
};
#ifdef CONFIG_DRIVER_TI_EMAC
static const struct pinmux_config emac_pins[] = {
/**
* rmii_hw_init
*
* DA850/OMAP-L138 EVM can interface to a daughter card for
* additional features. This card has an I2C GPIO Expander TCA6416
* to select the required functions like camera, RMII Ethernet,
* character LCD, video.
*
* Initialization of the expander involves configuring the
* polarity and direction of the ports. P07-P05 are used here.
* These ports are connected to a Mux chip which enables only one
* functionality at a time.
*
* For RMII phy to respond, the MII MDIO clock has to be disabled
* since both the PHY devices have address as zero. The MII MDIO
* clock is controlled via GPIO2[6].
*
* This code is valid for Beta version of the hardware
*/
int rmii_hw_init(void)
{
const struct pinmux_config gpio_pins[] = {
{ pinmux(6), 8, 1 }
};
u_int8_t buf[2];
unsigned int temp;
int ret;
/* PinMux for GPIO */
if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
return 1;
/* I2C Exapnder configuration */
/* Set polarity to non-inverted */
buf[0] = 0x0;
buf[1] = 0x0;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
return ret;
}
/* Configure P07-P05 as outputs */
buf[0] = 0x1f;
buf[1] = 0xff;
ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
if (ret) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* For Ethernet RMII selection
* P07(SelA)=0
* P06(SelB)=1
* P05(SelC)=1
*/
if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x read FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
buf[0] &= 0x1f;
buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
printf("\nExpander @ 0x%02x write FAILED!!!\n",
CONFIG_SYS_I2C_EXPANDER_ADDR);
}
/* Set the output as high */
temp = REG(GPIO_BANK2_REG_SET_ADDR);
temp |= (0x01 << 6);
REG(GPIO_BANK2_REG_SET_ADDR) = temp;
/* Set the GPIO direction as output */
temp = REG(GPIO_BANK2_REG_DIR_ADDR);
temp &= ~(0x01 << 6);
REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
return 0;
}
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "../common/misc.h"
#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi0_pins[] = {
{ pinmux(7), 1, 3 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(7), 1, 6 },
{ pinmux(7), 1, 7 }
};
#ifdef CONFIG_USE_NAND
/* EMIF-A bus pins for 8-bit NAND support on CS3 */
static const struct pinmux_config emifa_nand_pins[] = {
{ pinmux[13], 1, 6 },
{ pinmux[13], 1, 7 },
{ pinmux[14], 1, 0 },
{ pinmux[14], 1, 1 },
{ pinmux[14], 1, 2 },
{ pinmux[14], 1, 3 },
* the MAC address in EEPROM and warn on mismatch
*/
if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
printf("Warning: MAC address in EEPROM don't match "
"with the MAC address in the environment\n");
printf("Default using MAC address from environment\n");
}
#endif
return 0;
}
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
};
const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
#else
PINMUX_ITEM(emac_pins_mii),
#endif
#endif
#ifdef CONFIG_SPI_FLASH
PINMUX_ITEM(spi1_pins_base),
PINMUX_ITEM(spi1_pins_scs0),
#include <asm/io.h>
#include <asm/errno.h>
#include "../common/misc.h"
#include "common.h"
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi1_pins[] = {
{ pinmux(5), 1, 1 },
{ pinmux(5), 1, 2 },
{ pinmux(5), 1, 4 },
{ pinmux(5), 1, 5 }
};
#ifdef CONFIG_DAVINCI_MMC
/* MMC0 pin muxer settings */
const struct pinmux_config mmc0_pins[] = {
/* GP0[11] is required for SD to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
{ pinmux(10), 2, 0 }, /* MMCSD0_CLK */
{ pinmux(10), 2, 1 }, /* MMCSD0_CMD */
{ pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
{ pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
{ pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
static struct gpio_registry {
int is_registered;
char name[GPIO_NAME_SIZE];
} gpio_registry[MAX_NUM_GPIOS];
#if defined(CONFIG_SOC_DA8XX)
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
static const struct pinmux_config gpio_pinmux[] = {
{ pinmux(13), 8, 6 }, /* GP0[0] */
{ pinmux(13), 8, 7 },
{ pinmux(14), 8, 0 },
{ pinmux(14), 8, 1 },
{ pinmux(14), 8, 2 },
{ pinmux(14), 8, 3 },
{ pinmux(14), 8, 4 },
{ pinmux(14), 8, 5 },
{ pinmux(14), 8, 6 },
{ pinmux(14), 8, 7 },
{ pinmux(15), 8, 0 },
{ pinmux(15), 8, 1 },
{ pinmux(15), 8, 2 },
{ pinmux(15), 8, 3 },
{ pinmux(15), 8, 4 },
{ pinmux(15), 8, 5 },
dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
val = readl(PSC0_MDCTL + (15 * 4));
val |= 0x100;
writel(val, (PSC0_MDCTL + (15 * 4)));
}
int misc_init_r(void)
{
dspwake();
return 0;
}
static const struct pinmux_config gpio_pins[] = {
/* GP7[14] selects bootmode*/
{ pinmux(16), 8, 3 }, /* GP7[14] */
};
const struct pinmux_resource pinmuxes[] = {
#ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
#else
PINMUX_ITEM(emac_pins_mii),
#endif
#endif
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
PINMUX_ITEM(uart0_pins_txrx),
PINMUX_ITEM(uart0_pins_rtscts),
{ DAVINCI_LPSC_UART0 },
{ DAVINCI_LPSC_EMAC },
{ DAVINCI_LPSC_UART0 },
{ DAVINCI_LPSC_GPIO },
{ DAVINCI_LPSC_DDR_EMIF },
{ DAVINCI_LPSC_UART1 },
{ DAVINCI_LPSC_UART2 },
{ DAVINCI_LPSC_MMC_SD1 },
{ DAVINCI_LPSC_USB20 },
{ DAVINCI_LPSC_USB11 },
};
const int lpsc_size = ARRAY_SIZE(lpsc);
static const struct pinmux_config enbw_pins[] = {
{ pinmux(0), 8, 0 },
{ pinmux(0), 8, 1 },
{ pinmux(0), 8, 2 },
{ pinmux(0), 8, 3 },
{ pinmux(0), 8, 4 },
{ pinmux(0), 8, 5 },
{ pinmux(1), 4, 0 },
{ pinmux(1), 8, 1 },
{ pinmux(1), 8, 2 },
{ pinmux(1), 8, 3 },
{ pinmux(1), 8, 4 },
{ pinmux(1), 8, 5 },
{ pinmux(1), 8, 6 },
{ pinmux(1), 4, 7 },
{ pinmux(2), 8, 0 },
{ pinmux(5), 1, 0 },
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pinmux_defs.h>
/* SPI pin muxer settings */
const struct pinmux_config spi1_pins_base[] = {
{ pinmux(5), 1, 2 }, /* SPI1_CLK */
{ pinmux(5), 1, 4 }, /* SPI1_SOMI */
{ pinmux(5), 1, 5 }, /* SPI1_SIMO */
};
const struct pinmux_config spi1_pins_scs0[] = {
{ pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
};
/* UART pin muxer settings */
const struct pinmux_config uart0_pins_txrx[] = {
{ pinmux(3), 2, 4 }, /* UART0_RXD */
{ pinmux(3), 2, 5 }, /* UART0_TXD */
};
const struct pinmux_config uart1_pins_txrx[] = {
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
/* SPI0 pin muxer settings */
static const struct pinmux_config spi0_pins[] = {
{ pinmux(7), 1, 3 },
{ pinmux(7), 1, 4 },
{ pinmux(7), 1, 5 },
{ pinmux(7), 1, 6 },
{ pinmux(7), 1, 7 }
};
/* EMIF-A bus pins for 8-bit NAND support on CS3 */
static const struct pinmux_config emifa_nand_pins[] = {
{ pinmux(13), 1, 6 },
{ pinmux(13), 1, 7 },
{ pinmux(14), 1, 0 },
{ pinmux(14), 1, 1 },
{ pinmux(14), 1, 2 },
{ pinmux(14), 1, 3 },
{ pinmux(14), 1, 4 },