/*------------------------------------------------------------------------------*/
static void nand_recovery(void)
{
/*
* Configure PIOs
*/
const struct pio_desc bp4_pio[] = {
{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
pio_setup(bp4_pio);
/*
* If BP4 is pressed during Boot sequence
*/
/*
* Erase NandFlash block 0
*/
if (!pio_get_value(AT91C_PIN_PA(31)))
AT91F_NandEraseBlock0();
}
/*------------------------------------------------------------------------------*/
void sdramc_hw_init(void)
{
/*
* Configure PIOs
*/
const struct pio_desc sdramc_pio[] = {
{"D16", AT91C_PIN_PB(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D17", AT91C_PIN_PB(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D18", AT91C_PIN_PB(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D19", AT91C_PIN_PB(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D20", AT91C_PIN_PB(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D21", AT91C_PIN_PB(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D22", AT91C_PIN_PB(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D23", AT91C_PIN_PB(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D24", AT91C_PIN_PB(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D25", AT91C_PIN_PB(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D26", AT91C_PIN_PB(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D27", AT91C_PIN_PB(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D28", AT91C_PIN_PB(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D29", AT91C_PIN_PB(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D30", AT91C_PIN_PB(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D31", AT91C_PIN_PB(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the SDRAMC PIO controller to output PCK0
*/
pio_setup(sdramc_pio);
}
/*------------------------------------------------------------------------------*/
void df_recovery(AT91PS_DF pDf)
{
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
/*
* Configure PIOs
*/
const struct pio_desc bp4_pio[] = {
{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
pio_setup(bp4_pio);
/*
* If BP4 is pressed during Boot sequence
*/
/*
* Erase NandFlash block 0
*/
if (!pio_get_value(AT91C_PIN_PA(31)))
df_page_erase(pDf, 0);
#endif
}
void one_wire_hw_init(void)
{
const struct pio_desc wire_pio[] = {
{"1-Wire", AT91C_PIN_PB(18), 0, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(wire_pio);
}
static int ecb_at91_open(const char *dev,int voltage,int power_on,
const char *args[])
{
prog_init(NULL,NULL,NULL,&ecb_at91_bit);
if (power_on)
return -1;
if (!pio_map ())
return -1;
pio_setup();
pio_out(XRES,1);
pio_out(SCLK,0);
dummy = pio_in();
reset = 1;
return voltage;
}
/*------------------------------------------------------------------------------*/
void df_hw_init(void)
{
/*
* Configure PIOs
*/
const struct pio_desc df_pio[] = {
{"MISO", AT91C_PIN_PA(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PA(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PA(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS0", AT91C_PIN_PA(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the PIO controller
*/
pio_setup(df_pio);
}
/*------------------------------------------------------------------------------*/
void nandflash_hw_init(void)
{
/*
* Configure PIOs
*/
const struct pio_desc nand_pio[] = {
{"RDY_BSY", AT91C_PIN_PC(8), 0, PIO_PULLUP, PIO_INPUT},
{"NANDCS", AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface
*/
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM,
AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* EBI IO in 1.8V mode
*/
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) & ~(1 << 16),
AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SMC CS3
*/
writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(nand_pio);
nand_recovery();
}
/*---------------------------------------------------------------------------*/
void df_hw_init(void)
{
/*
* Configure PIOs for SPI0
*/
const struct pio_desc df_pio[] = {
{"MISO", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS0", AT91C_PIN_PA(14), 1, PIO_DEFAULT, PIO_OUTPUT}, /* Using GPIO as cs pin, set 1 is disable */
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(df_pio);
}
/*------------------------------------------------------------------------------*/
void df_hw_init(void)
{
/*
* Configure PIOs
*/
const struct pio_desc df_pio[] = {
{"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
{"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
{"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Configure the PIO controller
*/
pio_setup(df_pio);
}
/*------------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLL_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLL = 2 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller to output PCK0
*/
pio_setup(hw_pio);
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_VERBOSE */
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_MATRIX_SCFG4)) & ~0xFF) | 0x40, AT91C_MATRIX_SCFG4);
/*
* Initialize the matrix Slave 0 & Slave 4 (SRAM & EBI)
*/
writel(readl(AT91C_MATRIX_SCFG0) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG0);
writel(readl(AT91C_MATRIX_SCFG4) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG4);
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix
*/
writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_CCFG_EBICSA);
#ifdef MCK_100
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#else /* 133 MHz */
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif
#endif
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
cp15 |= I_CACHE;
set_cp15(cp15);
#ifdef CONFIG_SCLK
sclk_enable();
#endif
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
pio_setup(hw_pio);
/*
* Enable Debug messages on the DBGU
*/
#ifdef CONFIG_DEBUG
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif
#ifdef CONFIG_DDR2
/*
* Configure DDRAM Controller
*/
dbg_log(1, "Init DDR... ");
ddramc_hw_init();
dbg_log(1, "Done!\n\r");
#endif /* CONFIG_DDR2 */
}
/*------------------------------------------------------------------------------*/
void nandflash_hw_init(void)
{
unsigned int reg;
/*
* Configure PIOs
*/
const struct pio_desc nand_pio_hi[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(5), 0, PIO_PULLUP, PIO_INPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pio_lo[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A') {
reg &= ~AT91C_EBI_NFD0_ON_D16;
} else {
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
}
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SMC CS3
*/
writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
if (get_cm_rev() == 'A')
pio_setup(nand_pio_lo);
else
pio_setup(nand_pio_hi);
nand_recovery();
}
/*----------------------------------------------------------------------------*/
void hw_init(void)
{
unsigned int cp15;
/*
* Configure PIOs
*/
const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
{"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Disable watchdog
*/
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/*
* At this stage the main oscillator is supposed to be enabled
* * PCK = MCK = MOSC
*/
writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
/*
* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA
*/
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* PCK = PLLA/2 = 3 * MCK
*/
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Switch MCK on PLLA output
*/
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Configure PLLB
*/
pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure CP15
*/
cp15 = get_cp15();
//cp15 |= I_CACHE;
set_cp15(cp15);
/*
* Enable External Reset
*/
writel(AT91C_RSTC_KEY_UNLOCK
|| AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/*
* Configure the PIO controller
*/
pio_setup(hw_pio);
/*
* Configure the EBI Slave Slot Cycle to 64
*/
writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
(AT91C_BASE_MATRIX + MATRIX_SCFG3));
#ifdef CONFIG_DEBUG
/*
* Enable Debug messages on the DBGU
*/
dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
dbgu_print("Start AT91Bootstrap...\n\r");
#endif /* CONFIG_DEBUG */
#ifdef CONFIG_SDRAM
/*
* Initialize the matrix (memory voltage = 3.3)
*/
writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC |
(1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SDRAM Controller
*/
sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */
(MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif /* CONFIG_SDRAM */
}
