/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
*(misc_mem_clk_cntrl + 0) = 0xFF;
*(misc_mem_clk_cntrl + 1) = 0x00;
*(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;
/*
* Initialize ASF registers to an arbitrary address because someone
* long ago set things up this way inside the SPD read code. The
* SPD read code has been made generic and moved out of the board
* directory, so the ASF init is being done here.
*/
pm_iowrite(0x29, 0x80);
pm_iowrite(0x28, 0x61);
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
/*************************************************
* enable the dedicated function in lamar board.
*************************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
/*************************************************
* Dedicated mainboard function
*************************************************/
static void kahlee_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard "
CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
config_gpio_mux();
/* Power off unused clock pins of GPP PCIe devices */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
/* GPP CLK0-2 are connected to the 3 ethernet chips
* GPP CLK3-4 are connected to the miniPCIe slots */
write8(misc_mem_clk_cntrl + 0, 0x21);
write8(misc_mem_clk_cntrl + 1, 0x43);
/* GPP CLK5 is only connected to test pads -> disable */
write8(misc_mem_clk_cntrl + 2, 0x05);
/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
write8(misc_mem_clk_cntrl + 3, 0x00);
write8(misc_mem_clk_cntrl + 4, 0x00);
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
