static void pl181_fifo_run(pl181_state *s) { uint32_t bits; uint32_t value; int n; int limit; int is_read; is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0; if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card)) && !s->linux_hack) { limit = is_read ? PL181_FIFO_LEN : 0; n = 0; value = 0; while (s->datacnt && s->fifo_len != limit) { if (is_read) { value |= (uint32_t)sd_read_data(s->card) << (n * 8); n++; if (n == 4) { pl181_fifo_push(s, value); value = 0; n = 0; } } else { if (n == 0) { value = pl181_fifo_pop(s); n = 4; } sd_write_data(s->card, value & 0xff); value >>= 8; n--; } s->datacnt--; } if (n && is_read) { pl181_fifo_push(s, value); } }
static void pl181_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { pl181_state *s = (pl181_state *)opaque; switch (offset) { case 0x00: /* Power */ s->power = value & 0xff; break; case 0x04: /* Clock */ s->clock = value & 0xff; break; case 0x08: /* Argument */ s->cmdarg = value; break; case 0x0c: /* Command */ s->cmd = value; if (s->cmd & PL181_CMD_ENABLE) { if (s->cmd & PL181_CMD_INTERRUPT) { qemu_log_mask(LOG_UNIMP, "pl181: Interrupt mode not implemented\n"); } if (s->cmd & PL181_CMD_PENDING) { qemu_log_mask(LOG_UNIMP, "pl181: Pending commands not implemented\n"); } else { pl181_send_command(s); pl181_fifo_run(s); } /* The command has completed one way or the other. */ s->cmd &= ~PL181_CMD_ENABLE; } break; case 0x24: /* DataTimer */ s->datatimer = value; break; case 0x28: /* DataLength */ s->datalength = value & 0xffff; break; case 0x2c: /* DataCtrl */ s->datactrl = value & 0xff; if (value & PL181_DATA_ENABLE) { s->datacnt = s->datalength; pl181_fifo_run(s); } break; case 0x38: /* Clear */ s->status &= ~(value & 0x7ff); break; case 0x3c: /* Mask0 */ s->mask[0] = value; break; case 0x40: /* Mask1 */ s->mask[1] = value; break; case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */ case 0x90: case 0x94: case 0x98: case 0x9c: case 0xa0: case 0xa4: case 0xa8: case 0xac: case 0xb0: case 0xb4: case 0xb8: case 0xbc: if (s->datacnt == 0) { qemu_log_mask(LOG_GUEST_ERROR, "pl181: Unexpected FIFO write\n"); } else { pl181_fifo_push(s, value); pl181_fifo_run(s); } break; default: qemu_log_mask(LOG_GUEST_ERROR, "pl181_write: Bad offset %x\n", (int)offset); } pl181_update(s); }
static void pl181_fifo_run(pl181_state *s) { uint32_t bits; uint32_t value = 0; int n; int is_read; is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0; if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card)) && !s->linux_hack) { if (is_read) { n = 0; while (s->datacnt && s->fifo_len < PL181_FIFO_LEN) { value |= (uint32_t)sd_read_data(s->card) << (n * 8); s->datacnt--; n++; if (n == 4) { pl181_fifo_push(s, value); n = 0; value = 0; } } if (n != 0) { pl181_fifo_push(s, value); } } else { /* write */ n = 0; while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { if (n == 0) { value = pl181_fifo_pop(s); n = 4; } n--; s->datacnt--; sd_write_data(s->card, value & 0xff); value >>= 8; } } } s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO); if (s->datacnt == 0) { s->status |= PL181_STATUS_DATAEND; /* HACK: */ s->status |= PL181_STATUS_DATABLOCKEND; DPRINTF("Transfer Complete\n"); } if (s->datacnt == 0 && s->fifo_len == 0) { s->datactrl &= ~PL181_DATA_ENABLE; DPRINTF("Data engine idle\n"); } else { /* Update FIFO bits. */ bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE; if (s->fifo_len == 0) { bits |= PL181_STATUS_TXFIFOEMPTY; bits |= PL181_STATUS_RXFIFOEMPTY; } else { bits |= PL181_STATUS_TXDATAAVLBL; bits |= PL181_STATUS_RXDATAAVLBL; } if (s->fifo_len == 16) { bits |= PL181_STATUS_TXFIFOFULL; bits |= PL181_STATUS_RXFIFOFULL; } if (s->fifo_len <= 8) { bits |= PL181_STATUS_TXFIFOHALFEMPTY; } if (s->fifo_len >= 8) { bits |= PL181_STATUS_RXFIFOHALFFULL; } if (s->datactrl & PL181_DATA_DIRECTION) { bits &= PL181_STATUS_RX_FIFO; } else { bits &= PL181_STATUS_TX_FIFO; } s->status |= bits; } }