/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
* Init MTK propiartary log buffer control field.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
/* Enable non-secure access to CCI-400 registers */
mmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET, 0x1);
plat_cci_init();
plat_cci_enable();
if (gteearg.atf_log_buf_size != 0) {
INFO("mmap atf buffer : 0x%x, 0x%x\n\r",
gteearg.atf_log_buf_start,
gteearg.atf_log_buf_size);
mmap_add_region(
gteearg.atf_log_buf_start &
~(PAGE_SIZE_2MB_MASK),
gteearg.atf_log_buf_start &
~(PAGE_SIZE_2MB_MASK),
PAGE_SIZE_2MB,
MT_DEVICE | MT_RW | MT_NS);
INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n",
(gteearg.atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)),
PAGE_SIZE_2MB);
}
/*
* add TZRAM_BASE to memory map
* then set RO and COHERENT to different attribute
*/
plat_configure_mmu_el3(
(TZRAM_BASE & ~(PAGE_SIZE_MASK)),
(TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
/* Initialize for ATF log buffer */
if (gteearg.atf_log_buf_size != 0) {
gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
gteearg.atf_aee_debug_buf_start =
gteearg.atf_log_buf_start +
gteearg.atf_log_buf_size - ATF_AEE_BUFFER_SIZE;
INFO("ATF log service is registered (0x%x, aee:0x%x)\n",
gteearg.atf_log_buf_start,
gteearg.atf_aee_debug_buf_start);
} else{
gteearg.atf_aee_debug_buf_size = 0;
gteearg.atf_aee_debug_buf_start = 0;
}
/* Platform code before bl31_main */
/* compatible to the earlier chipset */
/* Show to ATF log buffer & UART */
INFO("BL3-1: %s\n", version_string);
INFO("BL3-1: %s\n", build_message);
}
void bl1_plat_arch_setup(void)
{
plat_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
BL_MEM_BASE, /* l-loader and BL1 ROM */
BL1_RO_LIMIT,
BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT);
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL_CODE_BASE,
BL_COHERENT_RAM_END - BL_CODE_BASE,
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
