// (tmr-delay ['num] 'num) -> Nil
any tmr_delay(any ex) {
timer_data_type period;
unsigned id = PLATFORM_TIMER_SYS_ID;
any x, y;
x = cdr(ex), y = EVAL(car(x));
if (plen(ex) == 1) {
// We only have 1 parameter. Assume
// *tmr-sys-timer* and get the time
// period.
NeedNum(ex, y);
period = (timer_data_type)unBox(y);
} else {
// Minimum 2 args required here - the
// id and the period. Ignore the others.
NeedNum(ex, y);
id = unBox(y);
MOD_CHECK_TIMER(ex, id);
x = cdr(x), y = EVAL(car(x));
NeedNum(ex, y);
period = unBox(y);
}
platform_timer_delay(id, period);
return Nil;
}
// Lua: delay( id, period )
static int tmr_delay( lua_State* L )
{
unsigned id, period;
id = luaL_checkinteger( L, 1 );
MOD_CHECK_ID( timer, id );
period = luaL_checkinteger( L, 2 );
platform_timer_delay( id, period );
return 0;
}
// Lua: delay( id, period )
static int tmr_delay( lua_State* L )
{
timer_data_type period;
unsigned id;
id = ( unsigned )luaL_optinteger( L, 1, PLATFORM_TIMER_SYS_ID );
MOD_CHECK_TIMER( id );
period = ( timer_data_type )luaL_checknumber( L, 2 );
platform_timer_delay( id, period );
return 0;
}
// Send one command to the keyboard
// Gets the command and the number of expected ACKs from ps2_send_buffer at
// the index received as argument
static void ps2h_send_cmd( int idx )
{
unsigned i;
int par;
int cmd = ps2_send_buffer[ idx * 2 ];
int nacks = ps2_send_buffer[ idx * 2 + 1 ];
platform_cpu_set_interrupt( INT_GPIO_NEGEDGE, PS2_CLOCK_PIN_RESNUM, PLATFORM_CPU_DISABLE );
ps2h_clock_low();
platform_timer_delay( PS2_TIMER_ID, 1000 );
ps2h_data_low();
ps2h_clock_high();
ps2h_wait_clock_hl();
for( i = par = 0; i < 8; i ++, cmd >>= 1 )
{
if( cmd & 1 )
{
ps2h_data_high();
par ++;
}
else
ps2h_data_low();
ps2h_wait_clock_hl();
}
// Send parity now
if( par & 1 )
ps2h_data_low();
else
ps2h_data_high();
ps2h_wait_clock_hl();
// Release data line (stop bit)
ps2h_data_high();
ps2h_wait_clock_hl();
// Read and interpret ACK bit
if( ps2h_data_get() == 1 ) // error, [TODO] what to do here?
{
}
while( ps2h_clock_get() == 0 );
// Clear pending interrupts and re-enable keyboard interrupt
ps2_acks_to_receive = nacks;
platform_cpu_get_interrupt_flag( INT_GPIO_NEGEDGE, PS2_CLOCK_PIN_RESNUM, PLATFORM_CPU_CLEAR_FLAG );
platform_cpu_set_interrupt( INT_GPIO_NEGEDGE, PS2_CLOCK_PIN_RESNUM, PLATFORM_CPU_ENABLE );
}
void initMAC( const u8* bytMacAddress )
{
pdata = bytMacAddress;
// Initialize the SPI and the CS pin
theclock = platform_spi_setup( ENC28J60_SPI_ID, PLATFORM_SPI_MASTER, ENC28J60_SPI_CLOCK, 0, 0, 8 );
platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_SET );
platform_pio_op( ENC28J60_CS_PORT, 1 << ENC28J60_CS_PIN, PLATFORM_IO_PIN_DIR_OUTPUT );
#if defined( ENC28J60_RESET_PORT ) && defined( ENC28J60_RESET_PIN )
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_CLEAR );
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_DIR_OUTPUT );
platform_timer_delay( 0, 30000 );
platform_pio_op( ENC28J60_RESET_PORT, 1 << ENC28J60_RESET_PIN, PLATFORM_IO_PIN_SET );
#endif
ResetMac(); // erm. Resets the MAC.
// setup memory by defining ERXST and ERXND
platform_timer_delay( 0, 20000 );
BankSel(0); // select bank 0
WriteCtrReg(ERXSTL,(u08)( RXSTART & 0x00ff));
WriteCtrReg(ERXSTH,(u08)((RXSTART & 0xff00)>> 8));
WriteCtrReg(ERXNDL,(u08)( RXEND & 0x00ff));
WriteCtrReg(ERXNDH,(u08)((RXEND & 0xff00)>>8));
// Make sure Rx Read ptr is at the start of Rx segment
WriteCtrReg(ERXRDPTL, (u08)( RXSTART & 0x00ff));
WriteCtrReg(ERXRDPTH, (u08)((RXSTART & 0xff00)>> 8));
BankSel(1); // select bank 1
WriteCtrReg(ERXFCON,( ERXFCON_UCEN + ERXFCON_CRCEN + ERXFCON_BCEN));
// Initialise the MAC registers
BankSel(2); // select bank 2
SetBitField(MACON1, MACON1_MARXEN); // Enable reception of frames
WriteCtrReg(MACLCON2, 63);
WriteCtrReg(MACON3, MACON3_FRMLNEN + // Type / len field will be checked
MACON3_TXCRCEN + // MAC will append valid CRC
MACON3_PADCFG0); // All small packets will be padded
SetBitField(MACON4, MACON4_DEFER);
WriteCtrReg(MAMXFLL, (u08)( MAXFRAMELEN & 0x00ff)); // set max frame len
WriteCtrReg(MAMXFLH, (u08)((MAXFRAMELEN & 0xff00)>>8));
WriteCtrReg(MABBIPG, 0x12); // back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGL , 0x12); // non back to back interpacket gap. set as per data sheet
WriteCtrReg(MAIPGH , 0x0C);
//Program our MAC address
BankSel(3);
WriteCtrReg(MAADR1,bytMacAddress[0]);
WriteCtrReg(MAADR2,bytMacAddress[1]);
WriteCtrReg(MAADR3,bytMacAddress[2]);
WriteCtrReg(MAADR4,bytMacAddress[3]);
WriteCtrReg(MAADR5,bytMacAddress[4]);
WriteCtrReg(MAADR6,bytMacAddress[5]);
// Initialise the PHY registes
WritePhyReg(PHCON1, 0x00);
WritePhyReg(PHCON2, PHCON2_HDLDIS);
WriteCtrReg(ECON1, ECON1_RXEN); //Enable the chip for reception of packets
SetBitField(EIE, EIE_INTIE);
WritePhyReg(PHIE, PHIE_PGEIE|PHIE_PLNKIE);
ReadPhyReg(PHIR);
}
void nrf_ll_delay_us( u32 delay )
{
platform_timer_delay( NRF24L01_TMR_ID, delay );
}
