void main()
{
//enum data_source ABC;
//ABC=PRBS7;
tChar temp;
lcd_init();
display("Initializing...");
enable_spi(0);
dac_set(0);
chip_init_CCFFE();
pll_init();
clearscr();
enable_serial();
display("Set Jumpers and ping");
temp = receive_serial();
clearscr();
display("Offset trim DUT1");
sel_source(OFFSET_CAL);
msDelay(1);
LF_SELECT = 0;
CHIP_RESET = 0;
// LF_SELECT=1;
while(1);
// {
// LF_SELECT=1;
// msDelay(10000);
// LF_SELECT=0;
// msDelay(10000);
// }
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52259 modules.
********************************************************/
asm
{
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
pll_init();
scm_init();
initialize_exceptions();
}
/*
* Out of reset, the low-level assembly code calls this routine to
* initialize the mcf5206e for this board. A temporary stack has been
* setup in the internal SRAM, and the stack pointer will be changed
* to point to DRAM once this routine returns.
*/
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52221 modules for the
* M522223EVB board.
********************************************************/
asm {
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
/* Set real time clock freq */
MCF_CLOCK_RTCDR = 48000000;
pll_init();
scm_init();
initialize_exceptions();
}
/** Low level init function.
*/
int __low_level_init(void) {
wdt_disable();
pll_init();
clock_enable();
return 1;
}
STATIC_PREFIX void memory_pll_init(int argc, char * argv[])
{
pll_init(&__plls); //running under default freq now . Before we fixed the PLL stable problem
__udelay(1000);//delay 1 ms , wait pll ready
serial_init(__plls.uart);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/*
* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regval;
enable_uart0_pin_mux();
regval = readl(&uart_base->uartsyscfg);
regval |= UART_RESET;
writel(regval, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
!= UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regval = readl(&uart_base->uartsyscfg);
regval |= UART_SMART_IDLE_EN;
writel(regval, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
enable_board_pin_mux();
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}
void spl_board_init(void)
{
bcu_init();
sbc_init();
sg_init();
uniphier_board_reset();
pll_init();
uniphier_board_init();
led_write(L, 0, , );
clkrst_init();
led_write(L, 1, , );
{
int res;
res = umc_init();
if (res < 0) {
while (1)
;
}
}
led_write(L, 2, , );
enable_dpll_ssc();
led_write(L, 3, , );
}
//-------------------------------------------------------------------
void notmain ( void )
{
pll_init();
uart_init();
hexstring(0x12345678,1);
hexstring(0x12345678,1);
}
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Setup global info */
#ifndef CONFIG_CMD_BURN
gd->arch.gi = &ginfo;
#else
gd->arch.gi = (struct global_info *)CONFIG_SPL_GINFO_BASE;
#endif
gpio_init();
#ifndef CONFIG_FPGA
/* Init uart first */
enable_uart_clk();
#endif
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
#ifndef CONFIG_FPGA
debug("Timer init\n");
timer_init();
#ifdef CONFIG_SPL_REGULATOR_SUPPORT
debug("regulator set\n");
spl_regulator_set();
#endif
debug("CLK stop\n");
clk_prepare();
debug("PLL init\n");
pll_init();
debug("CLK init\n");
clk_init();
#endif
debug("SDRAM init\n");
sdram_init();
debug("SDRAM init ok\n");
#ifdef CONFIG_DDR_TEST
ddr_basic_tests();
#endif
#ifndef CONFIG_BURNER
/* Clear the BSS */
memset(__bss_start, 0, (char *)&__bss_end - __bss_start);
debug("board_init_r\n");
board_init_r(NULL, 0);
#endif
}
void sys_init(void)
{
pll_init();
power_init();
vic_init();
SYS_SetFastGPIO();
gpio_init(test_handler);
i2c_init();
irq_enable();
}
PolyList *
pll_check_pointer(PolyList ** pll_pt)
{
assert(pll_pt);
PolyList * result= *pll_pt;
if (!result)
result= *pll_pt= pll_init(10);
return result;
}
void main (void)
{
// VectorInit(1); // change pointer to int vectors for test
pll_init(120); // Set the 5509 to 120MHz
OSInit(); /* Initialize MicroC/OS-II */
// printf ("Alpha port test for MicroC/OS-II for 5509-DSP.\n");
// printf (" Port to TI TMS320VC5509 \n");
// printf ("\n");
MySem =OSSemCreate(1);
err = OSTaskCreateExt(TaskStart,
(void *)0,
(void *)&TaskStartStk[TASKSTART_STK_SIZE-1],
10,
10,
(void *)(&TaskStartStk[0]),
TASKSTART_STK_SIZE,
(void *)&TaskStart_SStk[TASKSTART_SSTK_SIZE-1],
OS_TASK_OPT_STK_CLR + OS_TASK_OPT_STK_CHK);
OSTaskNameSet(0, "TaskStart", &err);
err = OSTaskCreateExt(Tasksecond,
(void *)0,
(void *)&Task2Stk[TASK_STK_SIZE-1],
11,
11,
(void *)(&Task2Stk[0]),
TASK_STK_SIZE,
(void *)&Task2_SStk[TASK_SSTK_SIZE-1],
OS_TASK_OPT_STK_CLR + OS_TASK_OPT_STK_CHK);
OSTaskNameSet(1, "TaskSecond", &err);
err = OSTaskCreateExt(Taskthird,
(void *)0,
(void *)&Task3Stk[TASK_STK_SIZE-1],
12,
12,
(void *)(&Task3Stk[0]),
TASK_STK_SIZE,
(void *)&Task3_SStk[TASK_SSTK_SIZE-1],
OS_TASK_OPT_STK_CLR + OS_TASK_OPT_STK_CHK);
OSTaskNameSet(2, "TaskThird", &err);
OSStart(); /* Start multitasking */
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
#ifdef CONFIG_SPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
wdt_disable();
/* Enable timer */
timer_init();
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* Set UART pins */
enable_uart0_pin_mux();
/* Set MMC pins */
enable_mmc1_pin_mux();
/* Set Ethernet pins */
enable_enet_pin_mux();
/* Enable UART */
uart_enable();
gd = &gdata;
preloader_console_init();
config_dmm(&evm_lisa_map_regs);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
#endif
}
PolyList *
pll_copy(PolyList * pll, void (*copy_method)(vec dest, const vec src))
{
if (!pll) return NULL;
PolyList * cp = pll_init(pll->size);
uint i;
for (i=0; i < pll->last; i++){
pll_append(&cp, pl_copy(pll->polys[i], copy_method, 1));
}
return cp;
}
void spl_board_init(void)
{
bcu_init();
sbc_init();
sg_init();
uniphier_board_reset();
pll_init();
uniphier_board_init();
led_write(L, 0, , );
memconf_init();
led_write(L, 1, , );
early_clkrst_init();
led_write(L, 2, , );
early_pin_init();
led_write(L, 3, , );
#ifdef CONFIG_SPL_SERIAL_SUPPORT
preloader_console_init();
#endif
led_write(L, 4, , );
{
int res;
res = umc_init();
if (res < 0) {
while (1)
;
}
}
led_write(L, 5, , );
enable_dpll_ssc();
led_write(L, 6, , );
}
void notmain ( void )
{
unsigned int ra,rb,rc,rd,re,rf;
unsigned int lastcount,nowcount;
pll_init();
//init GPIO
ra=GET8(FIO1DIR2);
ra|=0xB4;
PUT8(FIO1DIR2,ra);
ra=FIO1SET2;
rb=FIO1CLR2;
rc=0x80;
rd=0x20;
re=0x10;
rf=0x04;
PUT8(rb,rc);
PUT8(rb,rd);
PUT8(rb,re);
PUT8(rb,rf);
PUT32(T0PR,(120-1));
PUT32(T0CR,1); //enable timer
lastcount=GET32(T0TC);
while(1)
{
PUT8(ra,rc);
while(1)
{
nowcount=GET32(T0TC);
nowcount-=lastcount; //upcounter
if(nowcount>=25000000) break;
}
lastcount+=25000000;
PUT8(rb,rc);
while(1)
{
nowcount=GET32(T0TC);
nowcount-=lastcount; //upcounter
if(nowcount>=25000000) break;
}
lastcount+=25000000;
}
}
//-------------------------------------------------------------------
void notmain ( void )
{
unsigned int lastcount;
unsigned int nowcount;
unsigned int timeout;
pll_init(); //run clock at 60MHz.
PUT32(APBDIV,1); //run peripherals at 60MHz
uart_init();
hexstring(0x12345678,1);
//zero bits 30 and 31 (connect pin to GPIO)
PUT32(PINSEL0,GET32(PINSEL0)&(~(3<<(LEDBIT<<1))));
//make the pin an output
PUT32(IO0DIR,GET32(IO0DIR)|(1<<LEDBIT));
PUT32(T0CR,2); //reset timer
PUT32(T0CR,0); //reset timer
PUT32(T0PR,(1000000-1)); //divide by 1 million
PUT32(T0CR,1); //enable timer
timeout=60*3; //10 seconds
lastcount=GET32(T0TC);
while(1)
{
PUT32(IO0SET,(1<<LEDBIT));
//not too fast if you are just jamming these in
PUT32(U0THR,0x31);
while(1)
{
nowcount=GET32(T0TC);
nowcount-=lastcount; //upcounter
if(nowcount>=timeout) break;
}
lastcount+=timeout;
PUT32(IO0CLR,(1<<LEDBIT));
//not too fast if you are just jamming these in
PUT32(U0THR,0x30);
while(1)
{
nowcount=GET32(T0TC);
nowcount-=lastcount; //upcounter
if(nowcount>=timeout) break;
}
lastcount+=timeout;
}
}
void _bsp_platform_init(void)
{
/* Point the VTOR to the new copy of the vector table */
SCB_VTOR = (uint_32)___VECTOR_RAM;
NVICICPR2 = (1 << 9); // Clear any pending interrupts on USB
NVICISER2 = (1 << 9); // Enable interrupts from USB module
// Clear ACKISO
if (PMC_REGSC & PMC_REGSC_ACKISO_MASK)
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
/* init pll */
pll_init();
#ifdef MCGOUTCLK_72_MHZ
// USB Freq. Divider (Out. clk. = In. clk * (2/3))
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
#else
// USB Freq. Divider (Out. clk. = In. clk * (1/1))
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
#endif
// MCGPLLCLK clock selected as CLK source
SIM_SOPT2 |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK;
// USB Clock Gating
SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
#if(USE_MICRO_USB == TRUE)
/** USB 5V enable */
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; // Turn on PTC clocks
PORTC_PCR9 = (0 | PORT_PCR_MUX(1)); // Configure PTC9 pin as GPIO
GPIOC_PDDR |=(1<<9); // Set as output
GPIOC_PSOR =(1<<9);
#endif
// Weak pull-downs
USB0_USBCTRL = USB_USBCTRL_PDE_MASK;
}
void init(void)
{
MAMCR = 0x02; //Memory Acceleration enabled
MAMTIM = 0x04;
VPBDIV = 0x01; //0x01: peripheral frequency == cpu frequency, 0x00: per. freq. = crystal freq.
pll_init();
pll_feed();
init_ports();
#ifdef MATLAB
UART_Matlab_Initialize(57600);
#else
UARTInitialize(57600); //debug / command
#endif
UART1Initialize(57600); //57600 Servo / GPS, 38400 "indoor GPS"
init_spi();
init_spi1();
init_timer0();
// I2CInit(I2CMASTER);
PWM_Init();
ADCInit(ADC_CLK);
init_interrupts();
}
void kinetis_init(void)
{
#if PE_LDD_VERSION
/* Watchdog disabled by CPU bean (need to setup in CPU Inspector) */
__pe_initialize_hardware();
/* Enable clock to peripheral modules */
kinetis_clock_enable();
_bsp_mpu_disable();
/*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
PE_low_level_init();
#else
kinetis_wdt_disable();
pll_init();
/* Enable clock to peripheral modules */
kinetis_clock_enable();
_bsp_mpu_disable();
#endif
/* Initialize FlexBus */
_bsp_flexbus_setup();
/* Initialize MRAM */
_bsp_flexbus_mram_setup((uint_32)BSP_EXTERNAL_MRAM_RAM_BASE);
}
/*
* early system init of muxing and clocks.
*/
void beaglebone_sram_init(void)
{
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
beaglebone_config_ddr();
/* UART softreset */
uart_base = AM33XX_UART0_BASE;
regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
regVal |= UART_RESET;
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
/* Disable smart idle */
regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
regVal |= UART_SMART_IDLE_EN;
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
}
/*
* early system init of muxing and clocks.
*/
void s_init(u32 in_ddr)
{
/* Can be removed as A8 comes up with L2 enabled */
l2_cache_enable();
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
__raw_writel(0xAAAA, WDT_WSPR);
while(__raw_readl(WDT_WWPS) != 0x0);
__raw_writel(0x5555, WDT_WSPR);
while(__raw_readl(WDT_WWPS) != 0x0);
/* Setup the PLLs and the clocks for the peripherals */
#ifdef CONFIG_SETUP_PLL
pll_init();
#endif
#ifdef CONFIG_AM335X_CONFIG_DDR
if (!in_ddr)
config_am335x_ddr();
#endif
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the MCF52233 modules for the
* M52233DEMO board.
********************************************************/
asm
{
/* Initialize IPSBAR */
move.l #__IPSBAR,d0
andi.l #0xC0000000,d0 // need to mask
add.l #0x1,d0
move.l d0,0x40000000
/* Initialize FLASHBAR */
move.l #__FLASHBAR,d0
andi.l #0xFFF80000,d0 // need to mask
add.l #0x61,d0
movec d0,FLASHBAR
}
/*
* Allow interrupts from ABORT, SW1, SW2, and SW3 (IRQ[1,4,7,11])
*/
/* Enable IRQ signals on the port */
MCF_GPIO_PNQPAR = 0
| MCF_GPIO_PNQPAR_IRQ1_IRQ1
| MCF_GPIO_PNQPAR_IRQ4_IRQ4
| MCF_GPIO_PNQPAR_IRQ7_IRQ7;
MCF_GPIO_PGPPAR = 0
| MCF_GPIO_PGPPAR_IRQ11_IRQ11;
/* Set EPORT to look for rising edges */
MCF_EPORT0_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA1_RISING
| MCF_EPORT_EPPAR_EPPA4_RISING
| MCF_EPORT_EPPAR_EPPA7_RISING;
MCF_EPORT1_EPPAR = 0
| MCF_EPORT_EPPAR_EPPA11_RISING;
/* Clear any currently triggered events on the EPORT */
MCF_EPORT0_EPIER = 0
| MCF_EPORT_EPIER_EPIE1
| MCF_EPORT_EPIER_EPIE4
| MCF_EPORT_EPIER_EPIE7;
MCF_EPORT1_EPIER = 0
| MCF_EPORT_EPIER_EPIE11;
/* Enable interrupts in the interrupt controller */
MCF_INTC0_IMRL &= ~(0
| MCF_INTC_IMRL_INT_MASK1
| MCF_INTC_IMRL_INT_MASK4
| MCF_INTC_IMRL_INT_MASK7
| MCF_INTC_IMRL_MASKALL);
MCF_INTC1_IMRH &= ~(0
| MCF_INTC_IMRH_INT_MASK35);
MCF_INTC1_ICR35 = MCF_INTC_ICR_IL(4);
MCF_GPIO_PDDPAR = 0x0F;
/* Set real time clock freq */
MCF_CLOCK_RTCDR = 25000000;
/* Set GPIO for UART0 */
MCF_GPIO_PUAPAR = 0
| MCF_GPIO_PUAPAR_URXD0_URXD0
| MCF_GPIO_PUAPAR_UTXD0_UTXD0;
wtm_init();
pll_init();
scm_init();
initialize_exceptions();
}
EXPORT ER knl_init_device( void )
{
pll_init();
sio_init();
return E_OK;
}
/*************************************************************************
* 野火嵌入式开发工作室
*
* 函数名称：pll_init
* 功能说明：锁相环函数，用于设定频率。
* 参数说明：crystal_val 晶体选项，这里没用到
* 函数返回：无
* 修改时间：2012-1-20
* 备 注：根据 全局变量 mcg_div 保存的分频因子来分频
*************************************************************************/
unsigned char pll_init(clk_option opt)
{
unsigned char pll_freq;
if(opt != PLLUSR ) //自定义模式，直接加载全局变量mcg_div的值
{
//设置MCG时钟
switch(opt)
{
case PLL48:
mcg_div.prdiv = 24;
mcg_div.vdiv = 0;
break;
case PLL50:
mcg_div.prdiv = 24;
mcg_div.vdiv = 1;
break;
case PLL96:
mcg_div.prdiv = 24;
mcg_div.vdiv = 24;
break;
case PLL100:
mcg_div.prdiv = 24;
mcg_div.vdiv = 26;
break;
case PLL110:
mcg_div.prdiv = 24;
mcg_div.vdiv = 31;
break;
case PLL120:
mcg_div.prdiv = 19;
mcg_div.vdiv = 24;
break;
case PLL125:
mcg_div.prdiv = 19;
mcg_div.vdiv = 26;
break;
case PLL130:
mcg_div.prdiv = 19;
mcg_div.vdiv = 28;
break;
case PLL140:
mcg_div.prdiv = 14;
mcg_div.vdiv = 18;
break;
case PLL150:
mcg_div.prdiv = 14;
mcg_div.vdiv = 21;
break;
case PLL160:
mcg_div.prdiv = 14;
mcg_div.vdiv = 24;
break;
case PLL170:
mcg_div.prdiv = 14;
mcg_div.vdiv = 27;
break;
case PLL180:
mcg_div.prdiv = 14;
mcg_div.vdiv = 30;
break;
case PLL200:
mcg_div.prdiv = 12;
mcg_div.vdiv = 28;
break;
case PLL225:
mcg_div.prdiv = 11;
mcg_div.vdiv = 30;
break;
case PLL250:
mcg_div.prdiv = 10;
mcg_div.vdiv = 31;
break;
default:
return pll_init(PLL100); //这情况不会发生。
}
//设置分频
mcg_div.core_div = 0; // core = MCG
/* 这里提示警告，但是安全的，是为了安全才故意添加进去 */
if (opt <= 1 * MAX_BUS_CLK) mcg_div.bus_div = 0; // bus = MCG
else if(opt <= 2 * MAX_BUS_CLK) mcg_div.bus_div = 1; // bus = MCG/2
else if(opt <= 3 * MAX_BUS_CLK) mcg_div.bus_div = 2; // bus = MCG/3
else if(opt <= 4 * MAX_BUS_CLK) mcg_div.bus_div = 3; // bus = MCG/4 这里提示警告，不过没关系
else mcg_div.bus_div = 15; // bus = MCG/16
mcg_div.flex_div = mcg_div.bus_div; // flex = bus
/* 这里提示警告，但是安全的，是为了安全才故意添加进去 */
if (opt <= 1 * MAX_FLASH_CLK) mcg_div.flash_div = 0; // flash = MCG
else if(opt <= 2 * MAX_FLASH_CLK) mcg_div.flash_div = 1; // flash = MCG/2
else if(opt <= 3 * MAX_FLASH_CLK) mcg_div.flash_div = 2; // flash = MCG/3
else if(opt <= 4 * MAX_FLASH_CLK) mcg_div.flash_div = 3; // flash = MCG/4
else if(opt <= 5 * MAX_FLASH_CLK) mcg_div.flash_div = 4; // flash = MCG/5
else if(opt <= 6 * MAX_FLASH_CLK) mcg_div.flash_div = 5; // flash = MCG/6
else if(opt <= 7 * MAX_FLASH_CLK) mcg_div.flash_div = 6; // flash = MCG/7
else if(opt <= 8 * MAX_FLASH_CLK) mcg_div.flash_div = 7; // flash = MCG/8
else if(opt <= 9 * MAX_FLASH_CLK) mcg_div.flash_div = 8; // flash = MCG/9 这里提示警告，不过没关系
else if(opt <= 10 * MAX_FLASH_CLK) mcg_div.flash_div = 9; // flash = MCG/10
else mcg_div.flash_div = 15; // flash = MCG/16
}
pll_freq = (u8)(( (u16)50 * (u16)( mcg_div.vdiv + 24 )) / (u16)( mcg_div.prdiv + 1 ) ); // 50/ ( prdiv +1 ) * ( mcg_div.vdiv + 24 )
//上电复位后，单片机会自动进入 FEI 模式，使用 内部参考时钟
//为了使用外部时钟参考源，我们要先进入 FBE 模式:
#if (defined(K60_CLK) || defined(ASB817))
MCG_C2 = 0;
#else
// Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
#endif
//初始化晶振后释放锁定状态的振荡器和GPIO
SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
LLWU_CS |= LLWU_CS_ACKISO_MASK;
// Select external oscilator and Reference Divider and clear IREFS to start ext osc
// CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
/* if we aren't using an osc input we don't need to wait for the osc to init */
#if (!defined(K60_CLK) && !defined(ASB817))
while (!(MCG_S & MCG_S_OSCINIT_MASK)) {}; //等待晶振稳定
#endif
while (MCG_S & MCG_S_IREFST_MASK) {}; // wait for Reference clock Status bit to clear
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2) {}; // Wait for clock status bits to show clock source is ext ref clk
//进入FBE模式 分频后结果必须在 ：2 MHz ~ 4 MHz.
// n (n+1)分频 50M/(n+1) n为12~24之间
MCG_C5 = MCG_C5_PRDIV(mcg_div.prdiv); // prdiv +1 分频 ：2M
MCG_C6 = 0x0; // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
// 设置系统分频因子选项
//MCG=PLL, core = MCG/(mcg_div.core_div + 1), bus = MCG/(mcg_div.bus_div + 1),
//FlexBus = MCG/(mcg_div.flex_div + 1), Flash clock= MCG/(mcg_div.flash_div + 1)
set_sys_dividers(mcg_div.core_div, mcg_div.bus_div, mcg_div.flex_div, mcg_div.flash_div);
// Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
// n (n+24)倍频 n为0~31之间
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(mcg_div.vdiv) ; // mcg_div.vdiv + 1 倍频
while (!(MCG_S & MCG_S_PLLST_MASK)) {}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)) {}; // Wait for LOCK bit to set
// 现在已经进入了 PBE 模式
// Transition into PEE by setting CLKS to 0
// CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
MCG_C1 &= ~MCG_C1_CLKS_MASK;
// Wait for clock status bits to update
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) {};
// 现在已经进入了 PEE 模式
return pll_freq;
} //pll_init
int main()
{
int i;
#ifdef FPGA
pll_init();
#else
bt16_pll_init();
#endif
delay(500000);
uart_init((96000000/ 460800)); // pa8
puts(pubDate);
puts("...fpga bt16 setup ok.......\n");
#ifdef FPGA
spi_int();
#endif
puts("-----1\n");
system_init();
puts("-----2\n");
timer0_start();
puts("-----3\n");
RF_init();
//----------debug
HWI_Install(1, exception_isr, 3) ; //timer0_isr
ENABLE_INT();
puts("-----4\n");
thread_init(os_create_thread, os_delete_thread);
puts("-----5\n");
sys_timer_init();
puts("-----6\n");
ble_main();
btstack_main();
/* device_manager_init(); */
/*INTALL_HWI(BT_BLE_INT, le_hw_isr, 0);
INTALL_HWI(18, le_test_uart_isr, 0);*/
lbuf_init(malloc_buf, sizeof(malloc_buf)*4);
/* btstack_v21_main(); */
puts("------------4.0 start run loop-----------\n");
while(1)
{
int c;
//asm("idle");
/*delay(100000);*/
for (i=0; i<PRIORITY_NUM; i++)
{
if (thread_fun[i]){
thread_fun[i](i);
}
}
c = getchar();
switch(c)
{
case 'A':
puts("user cmd : ADV\n");
ble_set_adv();
break;
case 'S':
puts("user cmd : SCAN\n");
ble_set_scan();
break;
default:
break;
}
/*run_loop_execute();*/
/*printf("k");*/
}
return 0;
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
else if (board_is_evm_15_or_later())
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
void main()
{
int i=10,j,k,N=24;
tInt bias,scale;
tLong frequency;
tChar temp;
// __bit test_resultA;
FLG_CPL=0;
lcd_init();
display("Initializing...");
enable_spi(0);
dac_set(0);
chip_init_CCFFE();
pll_init();
clearscr();
enable_serial();
display("Set Jumpers and ping");
temp = receive_serial();
clearscr();
display(" CCFFE");
line2();
display("Throughput test");
msDelay(1000);
enable_serial();
load_test_data();
clearscr();
display("Setting up test");
line2();
display("With 7 bit PRBS");
scale = 2650/N;
for(i=N;i>0;i--)
{
for(j=0;j<20;j++)
{
chip_init_CCFFE();
sel_source(RING);
bias=scale*i;
dac_set(bias);
msDelay(1000);
for(k=j;k>=0;k--)
{
tick_RX_RC_CKIN();
msDelay(1);
}
frequency = fmeasure();
clearscr();
display("f(");
display_int(i);
display(",");
display_int(j);
display(")=");
display_freq(frequency);
write_test_data_CCFFE();
LF_SELECT = 0;
msDelay(1);
LF_SELECT = 1;
read_results_CCFFE();
test_result = cross_correlation();//source_data);
if(test_result)
{
FLG_CPL=1;
send_byte(fm_byte[0]);
send_byte(fm_byte[1]);
send_byte(fm_byte[2]);
send_int(i);
send_byte(',');
send_int(j);
}
}
}
clearscr();
display("Throughput test");
line2();
if(FLG_CPL)
display("SUCCESS");
else
display("Failed");
while(1);
}
static void sys_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
u32 sysclkctrl;
/* Set system state to SLOW */
sysclkctrl = readl(&misc_p->sys_clk_ctrl);
sysclkctrl &= ~SYS_MODE_MASK;
sysclkctrl |= XTAL_TIMEOUT_ENB | PLL_TIMEOUT_ENB | SYS_MODE_REQ_SLOW;
writel(sysclkctrl, &misc_p->sys_clk_ctrl);
writel(PLL_TIM, &misc_p->sys_clk_plltimer);
writel(OSCI_TIM, &misc_p->sys_clk_oscitimer);
#if defined(CONFIG_SPEAR1340)
u32 plgpio_enb_3;
/*
* The code below modifies plgpio_enb_3 register
* settings in order to add support for SPEAr1340
* rev AB DDR Board Modifications setting in output
* GPIOs 88 and 89 on GPIO controller.
*/
plgpio_enb_3 = readl(PLGPIO_ENB_3);
plgpio_enb_3 &= ~(PLGPIO_88_CFG | PLGPIO_89_CFG);
writel(plgpio_enb_3, PLGPIO_ENB_3);
u32 pad_pu_cfg_1, pad_pd_cfg_1;
/*
* The code below modifies pad_pu_cfg_1 and pad_pd_cfg_1
* registers settings in order to add support for SPEAr1340
* DDR Board Modifications:
* - DDR_PHY_1v2 (XGPIO 21: PullDown = 1, PullUp = 0)
* - DDR_PHY_1v5 (XGPIO 22: PullDown = 1, PullUp = 0)
*/
pad_pu_cfg_1 = readl(&misc_p->pad_pu_cfg_1);
pad_pu_cfg_1 |= (PAD_21_PU_CFG | PAD_22_PU_CFG);
writel(pad_pu_cfg_1, &misc_p->pad_pu_cfg_1);
pad_pd_cfg_1 = readl(&misc_p->pad_pd_cfg_1);
pad_pd_cfg_1 &= PAD_21_PD_CFG;
pad_pd_cfg_1 &= PAD_22_PD_CFG;
writel(pad_pd_cfg_1, &misc_p->pad_pd_cfg_1);
#elif (defined(CONFIG_SPEAR1310) && !defined(CONFIG_SPEAR1380_REVC))
/*
* Set the PAD function enable such that the PADs are routed to
* IP
*/
writel(readl(&misc_p->pad_function_en_1) | 0x300,
&misc_p->pad_function_en_1);
/*
* Set up the PAD direction in control of IP's / RAS by default
*/
writel(readl(&misc_p->pad_dir_sel_1) | 0x300,
&misc_p->pad_dir_sel_1);
#endif
/* Initialize PLLs */
pll_init();
mac_init();
/* Set system state to NORMAL */
sysclkctrl = readl(&misc_p->sys_clk_ctrl);
sysclkctrl &= ~SYS_MODE_MASK;
sysclkctrl |= XTAL_TIMEOUT_ENB | PLL_TIMEOUT_ENB | SYS_MODE_REQ_NORMAL;
writel(sysclkctrl, &misc_p->sys_clk_ctrl);
/* Wait for system to switch to normal mode */
while ((readl(&misc_p->sys_clk_ctrl) & SYS_STATE_MASK) !=
SYS_STATE_NORMAL);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
#ifdef CONFIG_NOR_BOOT
asm("stmfd sp!, {r2 - r4}");
asm("movw r4, #0x8A4");
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9");
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");
asm("ldmfd sp!, {r2 - r4}");
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
#if defined(CONFIG_NOR_BOOT)
/* NOR booting - enable serial console */
gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#else
gd = &gdata;
preloader_console_init();
#endif
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifndef CONFIG_NOR_BOOT
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
#endif
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
hang();
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
hang();
}
}
enable_board_pin_mux(&header);
if (!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
#ifdef CONFIG_NOR_BOOT
am33xx_spl_board_init();
#endif
/* The following boards are known to use DDR3. */
if ((!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) ||
(!strncmp("A33515BB", header.name, 8) &&
strncmp("1.5", header.version, 3) <= 0))
config_ddr(EMIF_REG_SDRAM_TYPE_DDR3);
else
config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
}
