Пример #1
0
/* set thermal config
 */
static void set_thermal_config(void)
{
	u8 byte;
	u16 word;
	device_t sm_dev;

	/* set ADT 7461 */
	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */

	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */

	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
	printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);

	/* sb600 settings for thermal config */
	/* set SB600 GPIO 64 to GPIO with pull-up */
	byte = pm2_ioread(0x42);
	byte &= 0x3f;
	pm2_iowrite(0x42, byte);

	/* set GPIO 64 to input */
	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
	word = pci_read_config16(sm_dev, 0x56);
	word |= 1 << 7;
	pci_write_config16(sm_dev, 0x56, word);

	/* set GPIO 64 internal pull-up */
	byte = pm2_ioread(0xf0);
	byte &= 0xee;
	pm2_iowrite(0xf0, byte);

	/* set Talert to be active low */
	byte = pm_ioread(0x67);
	byte &= ~(1 << 5);
	pm_iowrite(0x67, byte);

	/* set Talert to generate ACPI event */
	byte = pm_ioread(0x3c);
	byte &= 0xf3;
	pm_iowrite(0x3c, byte);

	/* THERMTRIP pin */
	/* byte = pm_ioread(0x68);
	 * byte |= 1 << 3;
	 * pm_iowrite(0x68, byte);
	 *
	 * byte = pm_ioread(0x55);
	 * byte |= 1 << 0;
	 * pm_iowrite(0x55, byte);
	 *
	 * byte = pm_ioread(0x67);
	 * byte &= ~( 1 << 6);
	 * pm_iowrite(0x67, byte);
	 */
}
Пример #2
0
void init_sb800_MANUAL_fans(struct device *dev)
{
	int i;
	struct southbridge_amd_cimx_sb800_config *sb_chip =
		(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);

	/* Init Fan 0 */
	if (sb_chip->fan0_enabled)
		for (i = 0; i < FAN_REGISTER_COUNT; i++)
			pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);

	/* Init Fan 1 */
	if (sb_chip->fan1_enabled)
		for (i = 0; i < FAN_REGISTER_COUNT; i++)
			pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);

	/* Init Fan 2 */
	if (sb_chip->fan2_enabled)
		for (i = 0; i < FAN_REGISTER_COUNT; i++)
			pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);

	/* Init Fan 3 */
	if (sb_chip->fan3_enabled)
		for (i = 0; i < FAN_REGISTER_COUNT; i++)
			pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);

	/* Init Fan 4 */
	if (sb_chip->fan4_enabled)
		for (i = 0; i < FAN_REGISTER_COUNT; i++)
			pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);

}
Пример #3
0
/*
 * set gpio40 gfx
 */
static void set_gpio40_gfx(void)
{
	u8 byte;
//	u16 word;
	u32 dword;
	device_t sm_dev;
	/* disable the GPIO40 as CLKREQ2# function */
	byte = pm_ioread(0xd3);
	byte &= ~(1 << 7);
	pm_iowrite(0xd3, byte);

	/* disable the GPIO40 as CLKREQ3# function */
	byte = pm_ioread(0xd4);
	byte &= ~(1 << 0);
	pm_iowrite(0xd4, byte);

	/* enable pull up for GPIO68 */
	byte = pm2_ioread(0xf1);
	byte &=	~(1 << 4);
	pm2_iowrite(0xf1, byte);

	/* access the smbus extended register */
	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));

	/*if the dev3 is present, set the gfx to 2x8 lanes*/
	/*otherwise set the gfx to 1x16 lanes*/
	if(is_dev3_present()){

		printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
		/* when the gpio40 is configured as GPIO, this will enable the output */
		pci_write_config32(sm_dev, 0xf8, 0x4);
		dword = pci_read_config32(sm_dev, 0xfc);
		dword &= ~(1 << 10);

	        /* When the gpio40 is configured as GPIO, this will represent the output value*/
		/* 1 :enable two x8  , 0 : master slot enable only */
		dword |= (1 << 26);
		pci_write_config32(sm_dev, 0xfc, dword);

	}else{
		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
		/* when the gpio40 is configured as GPIO, this will enable the output */
		pci_write_config32(sm_dev, 0xf8, 0x4);
		dword = pci_read_config32(sm_dev, 0xfc);
		dword &= ~(1 << 10);

        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
		/* 1 :enable two x8  , 0 : master slot enable only */
		dword &=  ~(1 << 26);
		pci_write_config32(sm_dev, 0xfc, dword);
	}
}
Пример #4
0
/*
 * set gpio40 gfx
 */
static void set_gpio40_gfx(void)
{
	u8 byte;
//	u16 word;
	u32 dword;
	struct device *sm_dev;
	/* disable the GPIO40 as CLKREQ2# function */
	byte = pm_ioread(0xd3);
	byte &= ~(1 << 7);
	pm_iowrite(0xd3, byte);

	/* disable the GPIO40 as CLKREQ3# function */
	byte = pm_ioread(0xd4);
	byte &= ~(1 << 0);
	pm_iowrite(0xd4, byte);

	/* enable pull up for GPIO68 */
	byte = pm2_ioread(0xf1);
	byte &=	~(1 << 4);
	pm2_iowrite(0xf1, byte);

	/* access the smbus extended register */
	sm_dev = pcidev_on_root(0x14, 0);

	/* set the gfx to 1x16 lanes */
	printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
	/* when the gpio40 is configured as GPIO, this will enable the output */
	pci_write_config32(sm_dev, 0xf8, 0x4);
	dword = pci_read_config32(sm_dev, 0xfc);
	dword &= ~(1 << 10);

        /* When the gpio40 is configured as GPIO, this will represent the output value*/
	/* 1 :enable two x8  , 0 : master slot enable only */
	dword &=  ~(1 << 26);
	pci_write_config32(sm_dev, 0xfc, dword);
}
Пример #5
0
/*
 * set thermal config
 */
static void set_thermal_config(void)
{
	u8 byte, byte2;
	u16 word;
	u32 dword;
	device_t sm_dev;

	/* set adt7475 */
	ADT7475_write_byte(0x40, 0x04);
	/* Config Register 6 */
	ADT7475_write_byte(0x10, 0x00);
	/* Config Register 7 */
	ADT7475_write_byte(0x11, 0x00);

	/* set Offset 64 format, enable THERM on Remote 1& Remote 2 */
	ADT7475_write_byte(0x7c, 0xa0);
	/* No offset for remote 2 */
	ADT7475_write_byte(0x72, 0x00);
	/* PWM 1 configuration register    CPU fan controlled by CPU Thermal Diode */
	ADT7475_write_byte(0x5c, 0x02);
	/* PWM 3 configuration register    Case fan controlled by 690 temp */
	ADT7475_write_byte(0x5e, 0x42);

	/* remote 1 low temp limit */
	ADT7475_write_byte(0x4e, 0x00);
	/* remote 1 High temp limit    (90C) */
	ADT7475_write_byte(0x4f, 0x9a);

	/* remote2 Low Temp Limit */
	ADT7475_write_byte(0x52, 0x00);
	/* remote2 High Limit    (90C) */
	ADT7475_write_byte(0x53, 0x9a);

	/*  remote 1 therm temp limit    (95C) */
	ADT7475_write_byte(0x6a, 0x9f);
	/* remote 2 therm temp limit    (95C) */
	ADT7475_write_byte(0x6c, 0x9f);

	/* PWM 1 minimum duty cycle     (37%) */
	ADT7475_write_byte(0x64, 0x60);
	/* PWM 1 Maximum duty cycle    (100%) */
	ADT7475_write_byte(0x38, 0xff);
	/* PWM 3 minimum duty cycle     (37%) */
	ADT7475_write_byte(0x66, 0x60);
	/* PWM 3 Maximum Duty Cycle    (100%) */
	ADT7475_write_byte(0x3a, 0xff);

	/*  Remote 1 temperature Tmin     (32C) */
	ADT7475_write_byte(0x67, 0x60);
	/* Remote 2 temperature Tmin     (32C) */
	ADT7475_write_byte(0x69, 0x60);
	/* remote 1 Trange            (53C ramp range) */
	ADT7475_write_byte(0x5f, 0xe8);
	/* remote 2 Trange            (53C ramp range) */
	ADT7475_write_byte(0x61, 0xe8);

	/* PWM2 Duty cycle */
	ADT7475_write_byte(0x65, 0x00);
	/* PWM2 Disabled */
	ADT7475_write_byte(0x5d, 0x80);
	/* PWM2 Max Duty Cycle */
	ADT7475_write_byte(0x39, 0x00);

	/* Config Register 3 - enable smbalert & therm */
	ADT7475_write_byte(0x78, 0x03);
	/* Config Register 4 - enable therm output */
	ADT7475_write_byte(0x7d, 0x09);
	/* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 2 fault, SmbAlert Fan for Therm Timer event */
	ADT7475_write_byte(0x75, 0x2a);
	/* Config Register 1 Set Start bit */
	ADT7475_write_byte(0x40, 0x05);
	/* Read status register to clear any old errors */
	byte2 = ADT7475_read_byte(0x42);
	byte = ADT7475_read_byte(0x41);

	/* remote 1 temperature offset */
	ADT7475_write_byte(0x70, 0x00);

	printk(BIOS_INFO, "Init adt7475 end , status 0x42 %02x, status 0x41 %02x\n",
		    byte2, byte);

	/* sb600 setting for thermal config. Set SB600 GPM5 to trigger ACPI event */
	/* set GPM5 as GPM5, not DDR3_memory disable */
	byte = pm_ioread(0x8f);
	byte |= 1 << 6;		/* enable GPE */
	pm_iowrite(0x8f, byte);

	/* GPM5 as GPIO not USB OC */
	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
	dword = pci_read_config32(sm_dev, 0x64);
	dword |= 1 << 19;
	pci_write_config32(sm_dev, 0x64, dword);

	/* Enable Client Management Index/Data registers */
	dword = pci_read_config32(sm_dev, 0x78);
	dword |= 1 << 11;	/* Cms_enable */
	pci_write_config32(sm_dev, 0x78, dword);

	/* MiscfuncEnable */
	byte = pci_read_config8(sm_dev, 0x41);
	byte |= (1 << 5);
	pci_write_config8(sm_dev, 0x41, byte);

	/* set GPM5 as input */
	/* set index register 0C50h to 13h (miscellaneous control) */
	outb(0x13, 0xC50);	/* CMIndex */
	/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
	byte = inb(0xC51);	/* CMData */
	byte &= 0x3f;
	byte |= 1 << 6;
	outb(byte, 0xC51);
	/* set GPM port 0C52h bit 5 to 1 to tri-state the GPM port */
	byte = inb(0xc52);	/* GpmPort */
	byte |= 1 << 5;
	outb(byte, 0xc52);
	/* set CM data register 0C51h bits [7:6] to 00b to set GPM port for read */
	byte = inb(0xc51);
	byte &= 0x3f;
	outb(byte, 0xc51);

	/* trigger SCI/SMI */
	byte = pm_ioread(0x34);
	byte &= 0xcf;
	pm_iowrite(0x34, byte);

	/* set GPM5 to not wake from s5 */
	byte = pm_ioread(0x77);
	byte &= ~(1 << 5);
	pm_iowrite(0x77, byte);

	/* trigger on falling edge */
	byte = pm_ioread(0x38);
	byte &= ~(1 << 2);
	pm_iowrite(0x38, byte);

	/* set SB600 GPIO 64 to GPIO with pull-up */
	byte = pm2_ioread(0x42);
	byte &= 0x3f;
	pm2_iowrite(0x42, byte);

	/* set GPIO 64 to input */
	word = pci_read_config16(sm_dev, 0x56);
	word |= 1 << 7;
	pci_write_config16(sm_dev, 0x56, word);

	/* set GPIO 64 internal pull-up */
	byte = pm2_ioread(0xf0);
	byte &= 0xee;
	pm2_iowrite(0xf0, byte);

	/* set Talert to be active low */
	byte = pm_ioread(0x67);
	byte &= ~(1 << 5);
	pm_iowrite(0x67, byte);

	/* set Talert to generate ACPI event */
	byte = pm_ioread(0x3c);
	byte &= 0xf3;
	pm_iowrite(0x3c, byte);

	/* THERMTRIP pin */
	/* byte = pm_ioread(0x68);
	 * byte |= 1 << 3;
	 * pm_iowrite(0x68, byte);
	 *
	 * byte = pm_ioread(0x55);
	 * byte |= 1 << 0;
	 * pm_iowrite(0x55, byte);
	 *
	 * byte = pm_ioread(0x67);
	 * byte &= ~( 1 << 6);
	 * pm_iowrite(0x67, byte);
	 */
}
Пример #6
0
/*
* SB700 enables all USB controllers by default in SMBUS Control.
* SB700 enables SATA by default in SMBUS Control.
*/
static void sm_init(device_t dev)
{
	u8 byte;
	u8 byte_old;
	u8 rev;
	u32 dword;
	void *ioapic_base;
	uint32_t power_state;
	uint32_t enable_legacy_usb;
	u32 nmi_option;

	printk(BIOS_INFO, "sm_init().\n");

	rev = get_sb700_revision(dev);
	/* This works in a similar fashion to a memory resource, but without an enable bit */
	ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));
	setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */

	enable_legacy_usb = 1;
	get_option(&enable_legacy_usb, "enable_legacy_usb");

	/* 2.10 Interrupt Routing/Filtering */
	byte = pci_read_config8(dev, 0x62);
	if (enable_legacy_usb)
		byte |= 0x3;
	else
		byte &= ~0x3;
	pci_write_config8(dev, 0x62, byte);

	byte = pci_read_config8(dev, 0x67);
	if (enable_legacy_usb)
		byte |= 0x1 << 7;
	else
		byte &= ~(0x1 << 7);
	pci_write_config8(dev, 0x67, byte);

	/* Delay back to back interrupts to the CPU. */
	dword = pci_read_config16(dev, 0x64);
	dword |= 1 << 13;
	pci_write_config16(dev, 0x64, dword);

	/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
	/* rpr 2.1 Enabling Legacy Interrupt */
	dword = pci_read_config8(dev, 0x62);
	dword |= 1 << 2;
	pci_write_config8(dev, 0x62, dword);

	dword = pci_read_config32(dev, 0x78);
	dword |= 1 << 9;
	pci_write_config32(dev, 0x78, dword);	/* enable 0xCD6 0xCD7 */

	/* bit 10: MultiMediaTimerIrqEn */
	dword = pci_read_config8(dev, 0x64);
	dword |= 1 << 10;
	pci_write_config8(dev, 0x64, dword);
	/* enable serial irq */
	byte = pci_read_config8(dev, 0x69);
	byte |= 1 << 7;		/* enable serial irq function */
	byte &= ~(0xF << 2);
	byte |= 4 << 2;		/* set NumSerIrqBits=4 */
	pci_write_config8(dev, 0x69, byte);

	/* Sx State Settings
	 * Note: These 2 registers need to be set correctly for the S-state
	 * to work properly. Otherwise the system may hang during resume
	 * from the S-state.
	 */
	/*Use 8us clock for delays in the S-state resume timing sequence.*/
	byte = pm_ioread(0x65);
	byte &= ~(1 << 7);
	pm_iowrite(0x65, byte);
	/* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
	byte = pm_ioread(0x68);
	byte |= 1 << 2;
	pm_iowrite(0x68, byte);

	/* IRQ0From8254 */
	byte = pci_read_config8(dev, 0x41);
	byte &= ~(1 << 7);
	pci_write_config8(dev, 0x41, byte);

	byte = pm_ioread(0x61);
	if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
		byte &= ~(1 << 1);	/* Clear for non-K8 CPUs */
	else
		byte |= 1 << 1;		/* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
	pm_iowrite(0x61, byte);

	/* disable SMI */
	byte = pm_ioread(0x53);
	byte |= 1 << 3;
	pm_iowrite(0x53, byte);

	/* power after power fail */
	power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
	get_option(&power_state, "power_on_after_fail");
	if (power_state > 2) {
		printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
		power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
	}
	byte = pm_ioread(0x74);
	byte &= ~0x03;
	if (power_state == POWER_MODE_OFF)
		byte |= 0x0;
	else if (power_state == POWER_MODE_ON)
		byte |= 0x1;
	else if (power_state == POWER_MODE_LAST)
		byte |= 0x2;
	byte |= 1 << 2;
	pm_iowrite(0x74, byte);
	printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]);

	byte = pm_ioread(0x68);
	byte &= ~(1 << 1);
	/* 2.7 */
	byte |= 1 << 2;
	pm_iowrite(0x68, byte);

	/* 2.7 */
	byte = pm_ioread(0x65);
	byte &= ~(1 << 7);
	pm_iowrite(0x65, byte);

	/* 2.16 */
	byte = pm_ioread(0x55);
	byte |= 1 << 5;
	pm_iowrite(0x55, byte);

	byte = pm_ioread(0xD7);
	byte |= 1 << 6 | 1 << 1;
	pm_iowrite(0xD7, byte);

	/* 2.15 */
	byte = pm_ioread(0x42);
	byte &= ~(1 << 2);
	pm_iowrite(0x42, byte);

	/* Set up NMI on errors */
	byte = inb(0x70);	/* RTC70 */
	byte_old = byte;
	nmi_option = NMI_OFF;
	get_option(&nmi_option, "nmi");
	if (nmi_option) {
		byte &= ~(1 << 7);	/* set NMI */
		printk(BIOS_INFO, "++++++++++set NMI+++++\n");
	} else {
		byte |= (1 << 7);	/* Can not mask NMI from PCI-E and NMI_NOW */
		printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
	}
	byte &= ~(1 << 7);
	if (byte != byte_old) {
		outb(byte, 0x70);
	}

	/*rpr v2.13  2.22 SMBUS PCI Config */
 	byte = pci_read_config8(dev, 0xE1);
	if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
		byte |= 1 << 0;
	}
	/*Set bit2 to 1, enable Io port 60h read/write SMi trapping and
	 *Io port 64h write Smi trapping. conflict with ps2 keyboard
	 */
	//byte |= 1 << 2 | 1 << 3 | 1 << 4;
	byte |= 1 << 3 | 1 << 4;
 	pci_write_config8(dev, 0xE1, byte);

	/* 2.5 Enabling Non-Posted Memory Write */
       	axindxc_reg(0x10, 1 << 9, 1 << 9);

	/* 2.11 IO Trap Settings */
	abcfg_reg(0x10090, 1 << 16, 1 << 16);

	/* ab index */
	pci_write_config32(dev, 0xF0, AB_INDX);
	/* Initialize the real time clock */
	cmos_init(0);

	/* 4.3 Enabling Upstream DMA Access */
	axcfg_reg(0x04, 1 << 2, 1 << 2);
	/* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
	abcfg_reg(0x10060, 9 << 17, 9 << 17);
	abcfg_reg(0x10064, 9 << 17, 9 << 17);

	/* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
	abcfg_reg(0x80, 1 << 0, 1<< 0);

	/* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
	/* 4.7 Enabling Additional Address Bits Checking in Downstream */
	/* 4.16 IO write and SMI ordering enhancement*/
	abcfg_reg(0x9c, 3 << 0, 3 << 0);
	if (REV_SB700_A12 == rev) {
		abcfg_reg(0x9c, 1 << 8, 1 << 8);
	} else if (rev >= REV_SB700_A14) {
		abcfg_reg(0x9c, 1 << 8, 0 << 8);
	}
	if (REV_SB700_A15 == rev) {
		abcfg_reg(0x90, 1 << 21, 1 << 21);
		abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15);
	}

	/* 4.8 Set B-Link Prefetch Mode */
	abcfg_reg(0x80, 3 << 17, 3 << 17);

	/* 4.9 Enabling Detection of Upstream Interrupts */
	abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);

	/* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
	 *  Transactions for the K8 Platform (for All Revisions) */
	abcfg_reg(0x10090, 1 << 8, 1 << 8);

	/* Set ACPI Software clock Throttling Period to 244 us*/
	byte = pm_ioread(0x68);
	byte &= ~(3 << 6);
	byte |= (2 << 6);	/* 244us */
	pm_iowrite(0x68, byte);

	if (REV_SB700_A15 == rev) {
		u16 word;

		/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
        	axindxc_reg(0x02, 1 << 9, 1 << 9);
		abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
		abcfg_reg(0x1009C, 0x00000030, 0x00000030);
		abcfg_reg(0x10090, 0x00001E00, 0x00001E00);

		/* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */
		abcfg_reg(0x58, 0x0000F800, 0x0000E800);

		/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
        	axindxc_reg(0x02, 1 << 10, 1 << 10);

		/* rpr v2.13 2.38 Unconditional Shutdown */
 		byte = pci_read_config8(dev, 0x43);
		byte &= ~(1 << 3);
 		pci_write_config8(dev, 0x43, byte);

		word = pci_read_config16(dev, 0x38);
		word |= 1 << 12;
 		pci_write_config16(dev, 0x38, word);

		byte |= 1 << 3;
 		pci_write_config8(dev, 0x43, byte);

		/* Enable southbridge MMIO decode */
		dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
		dword &= ~(0xffffff << 8);
		dword |= SB_MMIO_BASE_ADDRESS;
		dword |= 0x1;
		pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
	}
 	byte = pci_read_config8(dev, 0xAE);
 	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
 		byte |= 1 << 4;
	byte |= 1 << 5;	/* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
	byte |= 1 << 6;	/* Enable arbiter between APIC and PIC interrupts */
 	pci_write_config8(dev, 0xAE, byte);

	/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
	/* 4.12: Enabling AB and BIF Clock Gating */
	abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
	abcfg_reg(0x54, 0xFF << 16, 4 << 16);
	abcfg_reg(0x54, 1 << 24, 0 << 24);
	abcfg_reg(0x98, 0x0000FF00, 0x00004700);

	/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
	abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);

	/* 4.14:Enabling Requester ID for upstream traffic. */
	abcfg_reg(0x98, 1 << 16, 1 << 16);

	/* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
	byte = pm2_ioread(0xE5);
	byte |= 1 << 2;
	pm2_iowrite(0xE5, byte);

	/* Enable IDE controller. */
	byte = pm_ioread(0x59);
	byte &= ~(1 << 1);
	pm_iowrite(0x59, byte);

	/* Enable SCI as irq9. */
	outb(0x4, 0xC00);
	outb(0x9, 0xC01);

	printk(BIOS_INFO, "sm_init() end\n");

	/* Enable NbSb virtual channel */
	axcfg_reg(0x114, 0x3f << 1, 0 << 1);
	axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
	axcfg_reg(0x120, 7 << 24, 1 << 24);
	axcfg_reg(0x120, 1 << 31, 1 << 31);
	abcfg_reg(0x50, 1 << 3, 1 << 3);
}