Пример #1
0
//!
//! @brief This function initializes the hardware/software resources
//! required for device CDC task.
//!
void AK5394A_task_init(void)
{
	// Set up CS4344
	// Set up GLCK1 to provide master clock for CS4344
	gpio_enable_module_pin(GCLK1, GCLK1_FUNCTION);	// for DA_SCLK
													// LRCK is SCLK / 64 generated by TX_SSC
													// so SCLK of 6.144Mhz ===> 96khz

	pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
					  0,                  // osc_or_pll: use Osc (if 0) or PLL (if 1)
					  1,                  // pll_osc: select Osc0/PLL0 or Osc1/PLL1
					  1,                  // diven - enabled
					  0);                 // divided by 2.  Therefore GCLK1 = 6.144Mhz
	pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);

	pm_enable_osc1_ext_clock(&AVR32_PM);	// OSC1 is clocked by 12.288Mhz Osc
												// from AK5394A Xtal Oscillator
	pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);

	// Set up AK5394A
	gpio_clr_gpio_pin(AK5394_RSTN);		// put AK5394A in reset
	gpio_clr_gpio_pin(AK5394_DFS0);		// L L  -> 48khz
	gpio_clr_gpio_pin(AK5394_DFS1);
	gpio_set_gpio_pin(AK5394_HPFE);		// enable HP filter
	gpio_clr_gpio_pin(AK5394_ZCAL);		// use VCOML and VCOMR to cal
	gpio_set_gpio_pin(AK5394_SMODE1);	// SMODE1 = H for Master i2s
	gpio_set_gpio_pin(AK5394_SMODE2);	// SMODE2 = H for Master/Slave i2s

    gpio_set_gpio_pin(AK5394_RSTN);		// start AK5394A
    while (gpio_get_pin_value(AK5394_CAL)); // wait till CAL goes low

		// Assign GPIO to SSC.
	  gpio_enable_module(SSC_GPIO_MAP, sizeof(SSC_GPIO_MAP) / sizeof(SSC_GPIO_MAP[0]));
	  gpio_enable_pin_glitch_filter(SSC_RX_CLOCK);
	  gpio_enable_pin_glitch_filter(SSC_RX_DATA);
	  gpio_enable_pin_glitch_filter(SSC_RX_FRAME_SYNC);
	  gpio_enable_pin_glitch_filter(SSC_TX_CLOCK);
	  gpio_enable_pin_glitch_filter(SSC_TX_DATA);
	  gpio_enable_pin_glitch_filter(SSC_TX_FRAME_SYNC);

	  current_freq.frequency = 96000;

	  // set up SSC
	  ssc_i2s_init(ssc, 96000, 24, 32, SSC_I2S_MODE_STEREO_OUT_STEREO_IN, FPBA_HZ);

	  // set up PDCA
	  // In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix
	  // provides specific logic in order to re-arbitrate before the end of the INCR transfer.
	  //
	  // HSB Bus Matrix: By default the HSB bus matrix mode is in Undefined length burst type (INCR).
	  // Here we have to put in single access (the undefined length burst is treated as a succession of single
	  // accesses, allowing re-arbitration at each beat of the INCR burst.
	  // Refer to the HSB bus matrix section of the datasheet for more details.
	  //
	  // HSB Bus matrix register MCFG1 is associated with the CPU instruction master interface.
	  AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_CPU_INSN] = 0x1;

	  audio_buffer_in = 0;
	  spk_buffer_out = 0;
	  // Register PDCA IRQ interrupt.
	  pdca_set_irq();

	  // Init PDCA channel with the pdca_options.
	  pdca_init_channel(PDCA_CHANNEL_SSC_RX, &PDCA_OPTIONS); // init PDCA channel with options.
      pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
      pdca_init_channel(PDCA_CHANNEL_SSC_TX, &SPK_PDCA_OPTIONS); // init PDCA channel with options.
       pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_TX);

       //////////////////////////////////////////////
       // Enable now the transfer.
       pdca_enable(PDCA_CHANNEL_SSC_TX);


	  xTaskCreate(AK5394A_task,
              configTSK_AK5394A_NAME,
              configTSK_AK5394A_STACK_SIZE,
              NULL,
              configTSK_AK5394A_PRIORITY,
              NULL);

}
Пример #2
0
void board_init(void)
{
	
		// first change to OSC0 (12MHz)
		pm_enable_osc0_crystal(& AVR32_PM, FOSC0);            // Enable the Osc0 in crystal mode
		pm_enable_clk0(& AVR32_PM, OSC0_STARTUP);                  // Crystal startup time
		pm_switch_to_clock(& AVR32_PM, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
		
		
		
		pm_enable_osc1_ext_clock(& AVR32_PM);  // ocs1 is external clock
		pm_enable_clk1(& AVR32_PM, OSC1_STARTUP);
		
		pm_pll_setup(&AVR32_PM
		, 0   // pll
		, 3 // mul
		, 0 // div  ->  f_vfo = 16.384 MHz * 8 = 131.072 MHz
		, 1   // osc
		, 16  // lockcount
		);
		
		pm_pll_set_option(&AVR32_PM
		, 0 // pll
		, 1 // pll_freq  (f_vfo range 80MHz - 180 MHz)
		, 1 // pll_div2  (f_pll1 = f_vfo / 2)
		, 0 // pll_wbwdisable
		);
		
		pm_pll_enable(&AVR32_PM, 0);
		
		pm_wait_for_pll0_locked(&AVR32_PM);
		
		pm_cksel(&AVR32_PM
		, 1, 1 // PBA  (CPU / 4) = 16.384 MHz
		, 0, 0 // PBB  65.536 MHz
		, 0, 0 // HSB	 = CPU 65.536 MHz
		);
		
		flashc_set_wait_state(1);  // one wait state if CPU clock > 33 MHz
		
		pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); // switch to PLL0
		
		
		// --------------------------------------
		
		// USB clock
		
		// Use 12MHz from OSC0 and generate 96 MHz
		pm_pll_setup(&AVR32_PM, 1,  // pll.
		7,   // mul.
		1,   // div.
		0,   // osc.
		16); // lockcount.

		pm_pll_set_option(&AVR32_PM, 1, // pll.
		1,  // pll_freq: choose the range 80-180MHz.
		1,  // pll_div2.
		0); // pll_wbwdisable.

		// start PLL1 and wait forl lock
		pm_pll_enable(&AVR32_PM, 1);

		// Wait for PLL1 locked.
		pm_wait_for_pll1_locked(&AVR32_PM);

		pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,  // gc.
		1,  // osc_or_pll: use Osc (if 0) or PLL (if 1).
		1,  // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
		0,  // diven.
		0); // div.
		pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
		
		// --------------------------------------
	
	// LCD display
	
	gpio_enable_gpio( lcd_gpio_map, sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] ) );
	
	int i;
	
	for (i=0; i < (sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] )); i++)
	{
		gpio_configure_pin( lcd_gpio_map[i].pin, lcd_gpio_map[i].function);
	}
	
	
	gpio_enable_module( lcd_pwm_gpio_map, sizeof( lcd_pwm_gpio_map ) / sizeof( lcd_pwm_gpio_map[0] ) );
	
	
	// Backlight
	AVR32_PWM.channel[6].CMR.cpre = 3;
	AVR32_PWM.channel[6].cprd = 1000;
	AVR32_PWM.channel[6].cdty = 500;
	
	AVR32_PWM.ENA.chid6 = 1;
	
	// contrast
	AVR32_PWM.channel[0].CMR.cpre = 3;
	AVR32_PWM.channel[0].cprd = 1000;
	AVR32_PWM.channel[0].cdty = 520;
	
	AVR32_PWM.ENA.chid0 = 1;
	
	
	

	// switches

	gpio_enable_gpio( switch_gpio_map, sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] ) );
	
	for (i=0; i < (sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] )); i++)
	{
		gpio_configure_pin( switch_gpio_map[i].pin, switch_gpio_map[i].function);
	}
	
	
	// USART
	
	gpio_enable_module( usart_gpio_map, sizeof( usart_gpio_map ) / sizeof( usart_gpio_map[0] ) );
	
	
	
}